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Tue, 15 Nov 2016 13:27:16 +0000 From: Vladyslav Buslov To: Ferruh Yigit , "Ananyev, Konstantin" , "Richardson, Bruce" CC: "Wu, Jingjing" , "Zhang, Helin" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH] net/i40e: add additional prefetch instructions for bulk rx Thread-Index: AQHSDoto1p5CkxHiFkqgnkKWcmK4QKCh1pSAgAAeNcCAASdSAIAAAS4wgAD+E4CAAj3tgIAAAyuAgDP7Y4CAABKZIA== Date: Tue, 15 Nov 2016 13:27:16 +0000 Message-ID: References: <20160714172719.17502-1-vladyslav.buslov@harmonicinc.com> <20160714172719.17502-2-vladyslav.buslov@harmonicinc.com> <18156776-3658-a97d-3fbc-19c1a820a04d@intel.com> <9BB6961774997848B5B42BEC655768F80E277DFC@SHSMSX103.ccr.corp.intel.com> <2601191342CEEE43887BDE71AB9772583F0C0408@irsmsx105.ger.corp.intel.com> <2601191342CEEE43887BDE71AB9772583F0C09AD@irsmsx105.ger.corp.intel.com> <20161013101849.GA132256@bricha3-MOBL3> <2601191342CEEE43887BDE71AB9772583F0C1209@irsmsx105.ger.corp.intel.com> <7c26e964-f2c8-1685-829c-e1c37bb25bf3@intel.com> In-Reply-To: <7c26e964-f2c8-1685-829c-e1c37bb25bf3@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Vladyslav.Buslov@harmonicinc.com; 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Richardson, Bruce > Cc: Vladyslav Buslov; Wu, Jingjing; Zhang, Helin; dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH] net/i40e: add additional prefetch > instructions for bulk rx >=20 > On 10/13/2016 11:30 AM, Ananyev, Konstantin wrote: >=20 > <...> >=20 > >>>> > >>>> Actually I can see some valid use cases where it is beneficial to ha= ve this > prefetch in driver. > >>>> In our sw distributor case it is trivial to just prefetch next packe= t on > each iteration because packets are processed one by one. > >>>> However when we move this functionality to hw by means of > >>>> RSS/vfunction/FlowDirector(our long term goal) worker threads will > >> receive > >>>> packets directly from rx queues of NIC. > >>>> First operation of worker thread is to perform bulk lookup in hash > >>>> table by destination MAC. This will cause cache miss on accessing > >> each > >>>> eth header and can't be easily mitigated in application code. > >>>> I assume it is ubiquitous use case for DPDK. > >>> > >>> Yes it is a quite common use-case. > >>> Though I many cases it is possible to reorder user code to hide (or > minimize) that data-access latency. > >>> From other side there are scenarios where this prefetch is excessive = and > can cause some drop in performance. > >>> Again, as I know, none of PMDs for Intel devices prefetches packet's > data in simple (single segment) RX mode. > >>> Another thing that some people may argue then - why only one cache > >>> line is prefetched, in some use-cases might need to look at 2-nd one. > >>> > >> There is a build-time config setting for this behaviour for exactly > >> the reasons called out here - in some apps you get a benefit, in > >> others you see a perf hit. The default is "on", which makes sense for = most > cases, I think. > >> From common_base: > >> > >> CONFIG_RTE_PMD_PACKET_PREFETCH=3Dy$ > > > > Yes, but right now i40e and ixgbe non-scattered RX (both vector and sca= lar) > just ignore that flag. > > Though yes, might be a good thing to make them to obey that flag > properly. >=20 > Hi Vladyslav, >=20 > According Konstantin's comment, what do you think updating patch to do > prefetch within CONFIG_RTE_PMD_PACKET_PREFETCH ifdef? >=20 > But since config option is enabled by default, performance concern is sti= ll > valid and needs to be investigated. >=20 > Thanks, > ferruh Hi Ferruh, I'll update my patch according to code review suggestions. Regards, Vlad