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Tue, 14 Jan 2020 17:16:24 +0000 Received: from MWHPR11MB1807.namprd11.prod.outlook.com ([fe80::6548:ed5a:bf21:61de]) by MWHPR11MB1807.namprd11.prod.outlook.com ([fe80::6548:ed5a:bf21:61de%7]) with mapi id 15.20.2623.017; Tue, 14 Jan 2020 17:16:24 +0000 From: "Trahe, Fiona" To: "Kusztal, ArkadiuszX" , "dev@dpdk.org" CC: "akhil.goyal@nxp.com" , "Trahe, Fiona" Thread-Topic: [PATCH 1/2] crypto/qat: add chacha poly implementation Thread-Index: AQHVrGD8rz1WzABrqEibdkbj9Xxbv6fqmYWw Date: Tue, 14 Jan 2020 17:16:24 +0000 Message-ID: References: <20191206181336.6180-1-arkadiuszx.kusztal@intel.com> <20191206181336.6180-2-arkadiuszx.kusztal@intel.com> In-Reply-To: <20191206181336.6180-2-arkadiuszx.kusztal@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=fiona.trahe@intel.com; x-originating-ip: [192.198.151.179] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0eb8cbde-4c75-4ff7-5135-08d799157bd3 x-ms-traffictypediagnostic: MWHPR11MB1277: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0eb8cbde-4c75-4ff7-5135-08d799157bd3 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Jan 2020 17:16:24.6114 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JeHhC8VEy50AQCSC5cXyVo+8rOFYk336GTrAMPSD5MnOS5YSQGywbrzayJaD2My6fTZFoOuqYm9gvh2WrFwTSw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1277 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 1/2] crypto/qat: add chacha poly implementation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Arek, > -----Original Message----- > From: Kusztal, ArkadiuszX > Sent: Friday, December 6, 2019 6:14 PM > To: dev@dpdk.org > Cc: akhil.goyal@nxp.com; Trahe, Fiona ; Kusztal, A= rkadiuszX > > Subject: [PATCH 1/2] crypto/qat: add chacha poly implementation >=20 > This patchset adds Chacha20-Poly1305 implementation to Intel > QuickAssist Technology pmd. >=20 > Signed-off-by: Arek Kusztal > --- > doc/guides/cryptodevs/qat.rst | 1 + > doc/guides/rel_notes/release_20_02.rst | 4 ++++ > drivers/common/qat/qat_adf/icp_qat_hw.h | 17 ++++++++++++++-- > drivers/crypto/qat/qat_sym_capabilities.h | 32 +++++++++++++++++++++++++= ++++++ > drivers/crypto/qat/qat_sym_pmd.c | 11 ++++++++++- > drivers/crypto/qat/qat_sym_session.c | 20 +++++++++++++++---- > 6 files changed, 78 insertions(+), 7 deletions(-) [Fiona] The supported algorithm Matrix should be updated. This was missing = from the API patch, But can be added with this patch as this is the first PMD which is enabling= this algorithm. ///snip/// > diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat= /qat_adf/icp_qat_hw.h > index cef6486..ed04178 100644 > --- a/drivers/common/qat/qat_adf/icp_qat_hw.h > +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h > @@ -51,7 +51,10 @@ enum icp_qat_hw_auth_algo { > ICP_QAT_HW_AUTH_ALGO_SHA3_256 =3D 17, > ICP_QAT_HW_AUTH_RESERVED_3 =3D 18, > ICP_QAT_HW_AUTH_ALGO_SHA3_512 =3D 19, > - ICP_QAT_HW_AUTH_ALGO_DELIMITER =3D 20 > + ICP_QAT_HW_AUTH_ALGO_SHAKE_128 =3D 20, > + ICP_QAT_HW_AUTH_ALGO_SHAKE_256 =3D 21, > + ICP_QAT_HW_AUTH_ALGO_POLY =3D 22, [Fiona] I don't see anywhere these are used? Shouldn't they be? ///snip/// > +#define ICP_QAT_HW_CHACHAPOLY_ICV__SZ 16 [Fiona] typo double underscore. Need to update based on latest firmware hdr= s ///snip/// > diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qa= t_sym_session.c > index 72290ba..c6ca42c 100644 > --- a/drivers/crypto/qat/qat_sym_session.c > +++ b/drivers/crypto/qat/qat_sym_session.c > @@ -519,7 +519,8 @@ qat_sym_session_handle_single_pass(struct qat_sym_dev= _private *internals, > session->is_single_pass =3D 1; > session->min_qat_dev_gen =3D QAT_GEN3; > session->qat_cmd =3D ICP_QAT_FW_LA_CMD_CIPHER; > - session->qat_mode =3D ICP_QAT_HW_CIPHER_AEAD_MODE; > + if (aead_xform->algo =3D=3D RTE_CRYPTO_AEAD_AES_GCM) > + session->qat_mode =3D ICP_QAT_HW_CIPHER_AEAD_MODE; [Fiona] This fn should be reworked as now handling both chacha and gcm - co= mments only refer to GCM, and condition only checks GCM iv length - which i= s coincidentally matching chacha length. Several vars (is_single_pass, qat_= mode , qat_dev_gen) are set up before for chacha, then rewritten here. Best= do his only in fn and make clear what's common and what's different for ea= ch algo.=20 ///snip/// > @@ -746,15 +749,24 @@ qat_sym_session_configure_aead(struct rte_cryptodev= *dev, > session->qat_mode =3D ICP_QAT_HW_CIPHER_CTR_MODE; > session->qat_hash_alg =3D ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC; > break; > + case RTE_CRYPTO_AEAD_CHACHA20_POLY1305: > + if (aead_xform->key.length !=3D ICP_QAT_HW_CHACHAPOLY_KEY_SZ) > + return -EINVAL; > + session->qat_cipher_alg =3D ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305; > + session->qat_mode =3D ICP_QAT_HW_CIPHER_CTR_MODE; > + session->min_qat_dev_gen =3D QAT_GEN3; > + session->is_single_pass =3D 1; [Fiona] as comment above - combine these with the single-pass fn.=20 Maybe move call to handle_single_pass() into this switch statement? Also, I don't see qat_hash_alg set anywhere for CHACHA? Is this defaulting= to ALGO_NULL or missed? If default, better set explicitly as several other fns depend on this (get_= state1, get_digest_size, get_block_size).