From: Wathsala Wathawana Vithanage <wathsala.vithanage@arm.com>
To: Konstantin Ananyev <konstantin.ananyev@huawei.com>,
"dev@dpdk.org" <dev@dpdk.org>
Cc: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>,
"jerinj@marvell.com" <jerinj@marvell.com>,
"drc@linux.ibm.com" <drc@linux.ibm.com>, nd <nd@arm.com>,
nd <nd@arm.com>
Subject: RE: rte_ring move head question for machines with relaxed MO (arm/ppc)
Date: Wed, 9 Oct 2024 17:27:01 +0000 [thread overview]
Message-ID: <PAWPR08MB89098C4A273670A6935726909F7F2@PAWPR08MB8909.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <dd754772937b423c908be50653d93d1e@huawei.com>
> >
> > > > 1. rte_ring_generic_pvt.h:
> > > > =====================
> > > >
> > > > pseudo-c-code // related armv8 instructions
> > > > -------------------- --------------------------------------
> > > > head.load() // ldr [head]
> > > > rte_smp_rmb() // dmb ishld
> > > > opposite_tail.load() // ldr [opposite_tail]
> > > > ...
> > > > rte_atomic32_cmpset(head, ...) // ldrex[head];... stlex[head]
> > > >
> > > >
> > > > 2. rte_ring_c11_pvt.h
> > > > =====================
> > > >
> > > > pseudo-c-code // related armv8 instructions
> > > > -------------------- --------------------------------------
> > > > head.atomic_load(relaxed) // ldr[head]
> > > > atomic_thread_fence(acquire) // dmb ish
> > > > opposite_tail.atomic_load(acquire) // lda[opposite_tail]
> > > > ...
> > > > head.atomic_cas(..., relaxed) // ldrex[haed]; ... strex[head]
> > > >
> > > >
> > > > 3. rte_ring_hts_elem_pvt.h
> > > > ==========================
> > > >
> > > > pseudo-c-code // related armv8 instructions
> > > > -------------------- --------------------------------------
> > > > head.atomic_load(acquire) // lda [head]
> > > > opposite_tail.load() // ldr [opposite_tail]
> > > > ...
> > > > head.atomic_cas(..., acquire) // ldaex[head]; ... strex[head]
> > > >
> > > > The questions that arose from these observations:
> > > > a) are all 3 approaches equivalent in terms of functionality?
> > > Different, lda (Load with acquire semantics) and ldr (load) are different.
> >
> > I understand that, my question was:
> > lda {head]; ldr[tail]
> > vs
> > ldr [head]; dmb ishld; ldr [tail];
> >
> > Is there any difference in terms of functionality (memory ops
> ordering/observability)?
>
> To be more precise:
>
> lda {head]; ldr[tail]
> vs
> ldr [head]; dmb ishld; ldr [tail];
> vs
> ldr [head]; dmb ishld; lda [tail];
>
> what would be the difference between these 3 cases?
Case A: lda {head]; ldr[tail]
load of the head will be observed by the memory subsystem
before the load of the tail.
Case B: ldr [head]; dmb ishld; ldr [tail];
load of the head will be observed by the memory subsystem
Before the load of the tail.
Case C: ldr [head]; dmb ishld; lda [tail];
load of the head will be observed by the memory subsystem
before the load of the tail. In addition, any load or store program
order after lda[tail] will not be observed by the memory subsystem
before the load of the tail.
Essentially both cases A and B are the same.
They preserve following program orders.
LOAD-LOAD
LOAD-STORE
next prev parent reply other threads:[~2024-10-09 17:27 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-08 12:58 Konstantin Ananyev
2024-10-08 15:09 ` Wathsala Wathawana Vithanage
2024-10-08 15:12 ` Wathsala Wathawana Vithanage
2024-10-08 15:45 ` Konstantin Ananyev
2024-10-08 15:56 ` Konstantin Ananyev
2024-10-09 17:27 ` Wathsala Wathawana Vithanage [this message]
2024-10-10 16:54 ` Konstantin Ananyev
2024-10-11 0:11 ` Wathsala Wathawana Vithanage
2024-10-11 14:08 ` Konstantin Ananyev
2024-10-11 15:48 ` Wathsala Wathawana Vithanage
2024-10-15 15:11 ` Konstantin Ananyev
2024-10-09 1:41 ` Wathsala Wathawana Vithanage
2024-10-09 2:22 ` Wathsala Wathawana Vithanage
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