From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9382CA00C2; Tue, 27 Sep 2022 11:05:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F02041133; Tue, 27 Sep 2022 11:05:23 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 22FB8410D0 for ; Tue, 27 Sep 2022 11:05:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664269521; x=1695805521; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=N7heg7R7Pwh1yWHJxSHsBuxvGzgOPhlG+1FJG5cszyo=; b=X0X1p83VBSyqQ9euYW+HPuPHYXsV2EhhKghHSqO0xpMub9NDuzrjFAKt YMUoMr7R/KrgTKxKlu/9WI8IQoNJpeGFVFwbDAYlyGS/EqIpxBG3auYc6 Eo2qSmLudqBvXv0CRySgOiVbroY6AQSKFtAN/jbVmrb2+LSUeXrnAH8u8 8pq+sxdf7F282SrIaG5M+XOL/dOv/I5n262HfsnlVIghwIr//fjTtAeDB w5cV+M/JBF1+gvRiBoJAGXuz+hkKjmdb+FMBej1HuyGF24KQbqpGsECT9 t7tgIHB0ah4sIcl3Bq95gm4Xr7dvHXhXKlm8jpLXV/tDcjWWfVNuyn6wB Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="302175850" X-IronPort-AV: E=Sophos;i="5.93,348,1654585200"; d="scan'208";a="302175850" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2022 02:05:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10482"; a="763805888" X-IronPort-AV: E=Sophos;i="5.93,348,1654585200"; d="scan'208";a="763805888" Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16]) by fmsmga001.fm.intel.com with ESMTP; 27 Sep 2022 02:05:19 -0700 Received: from orsmsx608.amr.corp.intel.com (10.22.229.21) by ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 27 Sep 2022 02:05:18 -0700 Received: from orsmsx612.amr.corp.intel.com (10.22.229.25) by ORSMSX608.amr.corp.intel.com (10.22.229.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 27 Sep 2022 02:05:18 -0700 Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx612.amr.corp.intel.com (10.22.229.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31 via Frontend Transport; Tue, 27 Sep 2022 02:05:18 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (104.47.57.172) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.31; Tue, 27 Sep 2022 02:05:18 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZTiKO3l58VmL3C9X4hqIQVDMq0wLryx1EZIdy32qF8ROx//x/JP0XC9VRaJLZpzI2DtPu9qajZaKtt5gIuX3rJAi+wQblwEwj9aB0j3wFnmv5Kob+23gifYa906anvEwwPZCtzYb+vtt0JXfpcpj8kN2BfnkfTRmSAUdErRz/dI6SrfBE8gWbO/XhMs9k0Kf0yjWQnjxpujznaobCIaK0E0+PDGrIKqp+moJ2D4hzuE/RH3qspwTP5hIowOeJ5fCHn/nnRE55SmTa5wCify9lZb2yZTAr0nIQqOGCFiN849VRHXtexSzc34eUTmzG4S7oAwz7CV49TclQti5BsgjeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=v+m4FXhWwD3FHmC6wRuaP61qT+qbSPrYGe2/QJFqUQ0=; b=Wwgey/WTpYE3Ey3HFvzt0PJNyQZ8k49FJc3u4ZLXHl7x0XQ4sg/n/GMzYO0hq1ctGoxQVc9U0POtTdce3N6FETWAJzMUhjUACQXqEiRR24SPR9MykthIzMfSqvTDSF05klIKyRVTx2I5QDmOAqO6QQBR5W8VGePZkhwDVjxtjtmx6eIBNtzWCah7ejC1bg4ZF/y9oPUH9MM1ucppGtP9CpQJfM2oHtba+4DBpRgX0OMEfpkO26C2QZH7iRR4az7qgwGe6+hm7F+xSXcDl7waZwRSSuBky45+G2rl+SdyhI/lYwY3RsmWXXnEvPwNjqHIheXL0uV0vrZXJIgs1L1o4w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from PH0PR11MB5832.namprd11.prod.outlook.com (2603:10b6:510:141::7) by PH7PR11MB6833.namprd11.prod.outlook.com (2603:10b6:510:1ec::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.26; Tue, 27 Sep 2022 09:05:16 +0000 Received: from PH0PR11MB5832.namprd11.prod.outlook.com ([fe80::e9d1:3c1e:d9ed:57b2]) by PH0PR11MB5832.namprd11.prod.outlook.com ([fe80::e9d1:3c1e:d9ed:57b2%6]) with mapi id 15.20.5654.024; Tue, 27 Sep 2022 09:05:16 +0000 From: "Gujjar, Abhinandan S" To: Volodymyr Fialko , "dev@dpdk.org" , Jerin Jacob Kollanukkaran , Pavan Nikhilesh Bhagavatula , Shijith Thotton , "Hemant Agrawal" , Sachin Saxena , "Jayatheerthan, Jay" CC: Akhil Goyal , Anoob Joseph Subject: RE: [PATCH 1/3] eventdev: introduce event cryptodev vector type Thread-Topic: [PATCH 1/3] eventdev: introduce event cryptodev vector type Thread-Index: AQHYp+j7eGHDtoEzhEu4kLvCSEfnEK3ufXbQgANhlgCAAXEGYA== Date: Tue, 27 Sep 2022 09:05:16 +0000 Message-ID: References: <20220622013839.405771-1-vfialko@marvell.com> <20220804095907.97895-1-vfialko@marvell.com> <20220804095907.97895-2-vfialko@marvell.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.500.17 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5832:EE_|PH7PR11MB6833:EE_ x-ms-office365-filtering-correlation-id: 9ac7f4d5-ef8c-4f29-190b-08daa06764fa x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: kc+hYg1rykQoU0zC9VWyJAoluQAqEkJFZIKzXUBg8QfP7lFWQVQ5GtI4MaxlFdNzvMDyEyyT72kd6EPkYjkxv1WvbKfbjcekKMFK4TEf6H+1W422GBvmSi6400UFGBZXWOmbXMX03qTWkeRp4dRvAVWbGjZBfzceUl9HWxq4yUkCwdKrdu6kLqHDelAPbtFqxGDZSxTCgbi3/d8KYsECwdWVytOLjPXLQcJnvZUeJEnWehIfMR1p67cfMa2kQB20OGdCEsLQPP1Z8sjqDYp4bDXl9zqpBNDRogP3dgVgZfEsd5CVChpSs73HnhufmlMDB+Hc2K2J7ZZZ/4gPd9xguuxFmLmHTzggeHdw/ayo7j6af7Cw4Kz0bTqSiPGm7rgZOBgX7zp25lLjjlDfRgka7PjPTeusHMubHrGrwxKsfVpV46uQLk4cYERLB/Tw2o2/t+kTwiPDtQN5qe7A8biuj02EFapPzGA24A2tRqArmFE8nZUnoCvCFemqrROyRf7NnGtWHureKIL59Mbs6aXyNcrHJe+Ts9Lsmgv+qTGkBnpHYVxC7toeee4SAnIvYgyMB/Z0Jc4HPjNArLz0clWkRJwwBD8FbmE1Kibhyfrs3G1qZ+yBF2j4axb9bv427ehzKdw+2i3JrUozMXPQdEFXfVsdthtZKwpwxxj+BoNFWtcu51ZDGYcooIEI88jQVQr0tdfzEJXHyOVX0baqfa2NQktMTLCPYAW7c0O9fdFkSGFLg4qJ7Zw50DdawQJ/j0mmqT3jt6AZOWMtPbAkuFLYkQ== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:PH0PR11MB5832.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230022)(366004)(346002)(396003)(376002)(39860400002)(136003)(451199015)(5660300002)(478600001)(66556008)(52536014)(9686003)(64756008)(26005)(71200400001)(8936002)(38070700005)(38100700002)(30864003)(82960400001)(53546011)(76116006)(6506007)(66946007)(83380400001)(7696005)(41300700001)(66476007)(316002)(66446008)(4326008)(6636002)(54906003)(186003)(55016003)(110136005)(86362001)(33656002)(8676002)(122000001)(2906002)(579004)(559001); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?e0wQCb39pqlDlZijUwho5azrZPVBjtlumgL/KZZvdud+li6sWRziorPm5ym8?= =?us-ascii?Q?WaWD262FifzcSRshhxTh+s4uHu/LjUPX0Y0xgtQP4pRCTgAV033o0ytn1K4m?= =?us-ascii?Q?71n7UZDVamgg6otWnMKIHgS75pJ3meISH6DK5mLAf+u9XsccH9CVvJg/Tj7e?= =?us-ascii?Q?hpyEFiP5mtKm9+aYqApOuKVVIwdMInuhNl+juwIvEFVwcDYRV9E1wDnV9/ak?= =?us-ascii?Q?O4xlqFP0R3s9V30Adr7UH9WL41GOzNbdnuxD0fQyX3N/GcL1M0OdpAkZR0K2?= =?us-ascii?Q?6OOH93HlEiu/ZvV/ZidZdaYkrMnsN4/V08zCRa37toq+wyql5m55nRBMMhh0?= =?us-ascii?Q?XkjqBifxM4oXW8NJMMi6pAayVTggAcIcy3L0dXpVrUVVjRy86mWtlvkp6O/n?= =?us-ascii?Q?9nQuh1hhayFmjNB6YNW9w0q9ZGGNC67yz9KLHExInJMxpGmv47yqaTr4VKDW?= =?us-ascii?Q?W4Uyb75QxaYxl2vSI4xM0jxjxjz792H4lM4Z11jCVPbgdkdhujxF5yVfMSIP?= =?us-ascii?Q?6cR+1wXOJnTn81fepdQSfonYvIihgz+Ei0N7rfmIHTscp2jguxLzo9gmbtZy?= =?us-ascii?Q?oh0UPrBXeozadC7pvC0hNU1UU8ObbkSVxX8ykQFwrV+JgtrNd/kialjAjnBf?= =?us-ascii?Q?NqGcAhgF5sZWF+5Zc007L5PQklQEBl+jHSfbXDLrMIrqw+ab1cnPcaDpalUI?= =?us-ascii?Q?dzebGK0Ktc4q2BLmcv8obvrnUGtnJsQcuz7NhGjVl4Fc34CLUcBIAtwu1nhX?= =?us-ascii?Q?ZLPxBDc/FsGnvxwPyqyzhtYJQP7JRC3FbBL17FNP8+n5m0RE+nP/I+wFUMf/?= =?us-ascii?Q?bR88oHagTFH4vkj1mrUwNavBLqAMQW+dd8v/kvNOUo3SOAgArkdrt/Qzhq77?= =?us-ascii?Q?oJydvWI8wfiflyFiIo+e04hxYMchmvkC3PpyzhIKZ+nHrUMNS/mwf+242nfT?= =?us-ascii?Q?RawpJXaepXKG9305DvsIJy4pXXx4wLjOABpFN+fhcxvDFoglnO890cLz8juv?= =?us-ascii?Q?U81fZ60JE7IT1IpWDrpameuzvadJNKsDd2pwjkORB1Zs8VuJaHBQHQ27zd/c?= =?us-ascii?Q?rEUwBxvFyAwUqwc95DQTRYTTjG6i0eNqDYh6QY/wkDjPq9QLFl6OTHl6lXKQ?= =?us-ascii?Q?DRJTz0Jbi9U+LX2GYCTS5gfyDv8jTRoflezcKS1AmgxGITipurSGcQenP0fd?= =?us-ascii?Q?+OZ86f1SWTHj+ZjbjHXK9hjV0L78+0Z/hD0eIJBam6qCp1EMiOgAKDgmMplX?= =?us-ascii?Q?onYEyUMvf+n+QDN/7cmssYCOfIMqtaXfyU0jTquhp2yO2QVCH5k9AYVegt9t?= =?us-ascii?Q?fzwKO+R3MXDNIRPEB0+ZMMKTfnt5mqqk05N+ApiFqMNYfTryK74CliZvOpOy?= =?us-ascii?Q?GKEnT3U3d7xqbN51SdMVQMjay0QEvmf/Uv4HHsAVTpd4FHexu/SpyCkdcbfe?= =?us-ascii?Q?FIdwksgmAsDvphwNi6sgKLjO00PvOSA1AVWyAqFUmuSQQ1oEgIhqO0EzvEj7?= =?us-ascii?Q?ztnwlg4JVpdKOJ2+UEs4DlPcOBiuuQfRDM6nX7nZ2PEN6OHlDgq/P3Us7dOr?= =?us-ascii?Q?nRX38oNuz6ztMDn8QRm8kb6UHwgvc4JTwURNKF6sBPAA24oh87OkF/nV24nW?= =?us-ascii?Q?9g=3D=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5832.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9ac7f4d5-ef8c-4f29-190b-08daa06764fa X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Sep 2022 09:05:16.1894 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7NqS/1pHGEjUgxcWIVnc2sP8xyHqsveqK4/cSq5koHJ4zrIwRpXH59wR2AgWcWEJZSUYh1MKo8yKT2zvckmMLC4+4Ss2zS7ghbFe7iR95Sc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB6833 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Volodymyr Fialko > Sent: Monday, September 26, 2022 4:32 PM > To: Gujjar, Abhinandan S ; dev@dpdk.org; Jer= in > Jacob Kollanukkaran ; Pavan Nikhilesh Bhagavatula > ; Shijith Thotton ; > Hemant Agrawal ; Sachin Saxena > ; Jayatheerthan, Jay > > Cc: Akhil Goyal ; Anoob Joseph > Subject: RE: [PATCH 1/3] eventdev: introduce event cryptodev vector type >=20 >=20 >=20 > > -----Original Message----- > > From: Gujjar, Abhinandan S > > Sent: Saturday, September 24, 2022 10:44 AM > > To: Volodymyr Fialko ; dev@dpdk.org; Jerin Jacob > > Kollanukkaran ; Pavan Nikhilesh Bhagavatula > > ; Shijith Thotton ; > > Hemant Agrawal ; Sachin Saxena > > ; Jayatheerthan, Jay > > > > Cc: Akhil Goyal ; Anoob Joseph > > > > Subject: [EXT] RE: [PATCH 1/3] eventdev: introduce event cryptodev > > vector type > > > > External Email > > > > ---------------------------------------------------------------------- > > > > > > > -----Original Message----- > > > From: Volodymyr Fialko > > > Sent: Thursday, August 4, 2022 3:29 PM > > > To: dev@dpdk.org; Jerin Jacob ; Gujjar, > > > Abhinandan S ; Pavan Nikhilesh > > > ; Shijith Thotton ; > > > Hemant Agrawal ; Sachin Saxena > > > ; Jayatheerthan, Jay > > > > > > Cc: gakhil@marvell.com; anoobj@marvell.com; Volodymyr Fialko > > > > > > Subject: [PATCH 1/3] eventdev: introduce event cryptodev vector type > > > > > > Introduce ability to aggregate crypto operations processed by event > > > crypto adapter into single event containing rte_event_vector whose > > > event type is RTE_EVENT_TYPE_CRYPTODEV_VECTOR. > > > > > > Application should set RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR in > > > rte_event_crypto_adapter_queue_conf::flag and provide vector > > > configuration with respect of > > > rte_event_crypto_adapter_vector_limits, > > > which could be obtained by calling > > > rte_event_crypto_adapter_vector_limits_get, to enable vectorization. > > > > > > The event crypto adapter would be responsible for vectorizing the > > > crypto operations based on provided response information in > > > rte_event_crypto_metadata::response_info. > > > > > > Updated drivers and tests accordingly to new API. > > > > > > Signed-off-by: Volodymyr Fialko > > > --- > > > app/test-eventdev/test_perf_common.c | 10 +- > > > app/test/test_event_crypto_adapter.c | 12 ++- > > > .../prog_guide/event_crypto_adapter.rst | 23 +++- > > > drivers/event/cnxk/cn10k_eventdev.c | 4 +- > > > drivers/event/cnxk/cn9k_eventdev.c | 5 +- > > > drivers/event/dpaa/dpaa_eventdev.c | 9 +- > > > drivers/event/dpaa2/dpaa2_eventdev.c | 9 +- > > > drivers/event/octeontx/ssovf_evdev.c | 4 +- > > > lib/eventdev/eventdev_pmd.h | 35 +++++- > > > lib/eventdev/eventdev_trace.h | 6 +- > > > lib/eventdev/rte_event_crypto_adapter.c | 90 ++++++++++++++-- > > > lib/eventdev/rte_event_crypto_adapter.h | 101 ++++++++++++++++= +- > > > lib/eventdev/rte_event_eth_rx_adapter.h | 3 +- > > > lib/eventdev/rte_eventdev.h | 8 ++ > > > 14 files changed, 276 insertions(+), 43 deletions(-) > > > > > > > I don't see dataplane implementation of vectorization in the crypto ada= pter! > > Is it missed out in the patch? > > comments inline. > > > Right now we are targeting crypto_cn10k PMD and ipsec-secgw event mode to > support vectorization. Is there a way to test this? When can be dataplane changes expected? >=20 > > > diff --git a/app/test-eventdev/test_perf_common.c b/app/test- > > > eventdev/test_perf_common.c index 81420be73a..c770bc93f6 100644 > > > --- a/app/test-eventdev/test_perf_common.c > > > +++ b/app/test-eventdev/test_perf_common.c > > > @@ -837,14 +837,14 @@ perf_event_crypto_adapter_setup(struct > > > test_perf *t, struct prod_data *p) > > > } > > > > > > if (cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { > > > - struct rte_event response_info; > > > + struct rte_event_crypto_adapter_queue_conf conf; > > > > > > - response_info.event =3D 0; > > > - response_info.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > > > - response_info.queue_id =3D p->queue_id; > > > + memset(&conf, 0, sizeof(conf)); > > > + conf.ev.sched_type =3D RTE_SCHED_TYPE_ATOMIC; > > > + conf.ev.queue_id =3D p->queue_id; > > > ret =3D rte_event_crypto_adapter_queue_pair_add( > > > TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id, > > > - &response_info); > > > + &conf); > > > } else { > > > ret =3D rte_event_crypto_adapter_queue_pair_add( > > > TEST_PERF_CA_ID, p->ca.cdev_id, p->ca.cdev_qp_id, > NULL); diff > > > --git a/app/test/test_event_crypto_adapter.c > > > b/app/test/test_event_crypto_adapter.c > > > index 2ecc7e2cea..bb617c1042 100644 > > > --- a/app/test/test_event_crypto_adapter.c > > > +++ b/app/test/test_event_crypto_adapter.c > > > @@ -1175,6 +1175,10 @@ test_crypto_adapter_create(void) static int > > > test_crypto_adapter_qp_add_del(void) > > > { > > > + struct rte_event_crypto_adapter_queue_conf queue_conf =3D { > > > + .ev =3D response_info, > > > + }; > > > + > > > uint32_t cap; > > > int ret; > > > > > > @@ -1183,7 +1187,7 @@ test_crypto_adapter_qp_add_del(void) > > > > > > if (cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { > > > ret =3D > > > rte_event_crypto_adapter_queue_pair_add(TEST_ADAPTER_ID, > > > - TEST_CDEV_ID, TEST_CDEV_QP_ID, > > > &response_info); > > > + TEST_CDEV_ID, TEST_CDEV_QP_ID, > > > &queue_conf); > > > } else > > > ret =3D > > > rte_event_crypto_adapter_queue_pair_add(TEST_ADAPTER_ID, > > > TEST_CDEV_ID, TEST_CDEV_QP_ID, > NULL); @@ -1206,6 +1210,10 @@ > > > configure_event_crypto_adapter(enum > > > rte_event_crypto_adapter_mode mode) > > > .new_event_threshold =3D 1200, > > > }; > > > > > > + struct rte_event_crypto_adapter_queue_conf queue_conf =3D { > > > + .ev =3D response_info, > > > + }; > > > + > > > uint32_t cap; > > > int ret; > > > > > > @@ -1238,7 +1246,7 @@ configure_event_crypto_adapter(enum > > > rte_event_crypto_adapter_mode mode) > > > > > > if (cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { > > > ret =3D > > > rte_event_crypto_adapter_queue_pair_add(TEST_ADAPTER_ID, > > > - TEST_CDEV_ID, TEST_CDEV_QP_ID, > > > &response_info); > > > + TEST_CDEV_ID, TEST_CDEV_QP_ID, > > > &queue_conf); > > > } else > > > ret =3D > > > rte_event_crypto_adapter_queue_pair_add(TEST_ADAPTER_ID, > > > TEST_CDEV_ID, TEST_CDEV_QP_ID, NULL); diff > --git > > > a/doc/guides/prog_guide/event_crypto_adapter.rst > > > b/doc/guides/prog_guide/event_crypto_adapter.rst > > > index 4fb5c688e0..554df7e358 100644 > > > --- a/doc/guides/prog_guide/event_crypto_adapter.rst > > > +++ b/doc/guides/prog_guide/event_crypto_adapter.rst > > > @@ -201,10 +201,10 @@ capability, event information must be passed > > > to the add API. > > > > > > ret =3D rte_event_crypto_adapter_caps_get(id, evdev, &cap); > > > if (cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) { > > > - struct rte_event event; > > > + struct rte_event_crypto_adapter_queue_conf conf; > > > > > > - // Fill in event information & pass it to add API > > > - rte_event_crypto_adapter_queue_pair_add(id, cdev_id,= qp_id, > > > &event); > > > + // Fill in conf.event information & pass it to add A= PI > > > + rte_event_crypto_adapter_queue_pair_add(id, > > > + cdev_id, qp_id, &conf); > > > } else > > > rte_event_crypto_adapter_queue_pair_add(id, > > > cdev_id, qp_id, NULL); > > > > > > @@ -291,6 +291,23 @@ the ``rte_crypto_op``. > > > rte_memcpy(op + len, &m_data, sizeof(m_data)); > > > } > > > > > > +Enable event vectorization > > > +~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > + > > > +The event crypto adapter can aggregate outcoming crypto operations > > > +based on provided response information of > > > +``rte_event_crypto_metadata::response_info`` > > > +and generate a ``rte_event`` containing ``rte_event_vector`` whose > > > +event type is ``RTE_EVENT_TYPE_CRYPTODEV_VECTOR``. > > > +To enable vectorization application should set > > > +RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR in > > > +``rte_event_crypto_adapter_queue_conf::flag`` and provide vector > > > +configuration(size, mempool, etc.) with respect of > > > +``rte_event_crypto_adapter_vector_limits``, which could be obtained > > > +by calling ``rte_event_crypto_adapter_vector_limits_get()``. > > > + > > > +The RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR capability > indicates > > > +whether PMD supports this feature. > > > + > > > Start the adapter instance > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > diff --git a/drivers/event/cnxk/cn10k_eventdev.c > > > b/drivers/event/cnxk/cn10k_eventdev.c > > > index 5a0cab40a9..e74ec57382 100644 > > > --- a/drivers/event/cnxk/cn10k_eventdev.c > > > +++ b/drivers/event/cnxk/cn10k_eventdev.c > > > @@ -889,11 +889,11 @@ static int > > > cn10k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev, > > > const struct rte_cryptodev *cdev, > > > int32_t queue_pair_id, > > > - const struct rte_event *event) > > > + const struct rte_event_crypto_adapter_queue_conf > > > *conf) > > > { > > > struct cnxk_sso_evdev *dev =3D cnxk_sso_pmd_priv(event_dev); > > > > > > - RTE_SET_USED(event); > > > + RTE_SET_USED(conf); > > > > > > CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn10k"); > > > CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn10k"); diff -- > > > git a/drivers/event/cnxk/cn9k_eventdev.c > > > b/drivers/event/cnxk/cn9k_eventdev.c > > > index 2e27030049..45ed547cb0 100644 > > > --- a/drivers/event/cnxk/cn9k_eventdev.c > > > +++ b/drivers/event/cnxk/cn9k_eventdev.c > > > @@ -1120,11 +1120,12 @@ cn9k_crypto_adapter_caps_get(const struct > > > rte_eventdev *event_dev, static int > > > cn9k_crypto_adapter_qp_add(const struct rte_eventdev *event_dev, > > > const struct rte_cryptodev *cdev, > > > - int32_t queue_pair_id, const struct rte_event *event) > > > + int32_t queue_pair_id, > > > + const struct rte_event_crypto_adapter_queue_conf > > > *conf) > > > { > > > struct cnxk_sso_evdev *dev =3D cnxk_sso_pmd_priv(event_dev); > > > > > > - RTE_SET_USED(event); > > > + RTE_SET_USED(conf); > > > > > > CNXK_VALID_DEV_OR_ERR_RET(event_dev->dev, "event_cn9k"); > > > CNXK_VALID_DEV_OR_ERR_RET(cdev->device, "crypto_cn9k"); diff --git > > > a/drivers/event/dpaa/dpaa_eventdev.c > > > b/drivers/event/dpaa/dpaa_eventdev.c > > > index ff6cc0be18..2b9ecd9fbf 100644 > > > --- a/drivers/event/dpaa/dpaa_eventdev.c > > > +++ b/drivers/event/dpaa/dpaa_eventdev.c > > > @@ -26,6 +26,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include #include > > > #include @@ -775,10 > > > +776,10 @@ static int dpaa_eventdev_crypto_queue_add(const struct > > > rte_eventdev *dev, > > > const struct rte_cryptodev *cryptodev, > > > int32_t rx_queue_id, > > > - const struct rte_event *ev) > > > + const struct rte_event_crypto_adapter_queue_conf *conf) > > > { > > > struct dpaa_eventdev *priv =3D dev->data->dev_private; > > > - uint8_t ev_qid =3D ev->queue_id; > > > + uint8_t ev_qid =3D conf->ev.queue_id; > > > u16 ch_id =3D priv->evq_info[ev_qid].ch_id; > > > int ret; > > > > > > @@ -786,10 +787,10 @@ dpaa_eventdev_crypto_queue_add(const struct > > > rte_eventdev *dev, > > > > > > if (rx_queue_id =3D=3D -1) > > > return dpaa_eventdev_crypto_queue_add_all(dev, > > > - cryptodev, ev); > > > + cryptodev, &conf->ev); > > > > > > ret =3D dpaa_sec_eventq_attach(cryptodev, rx_queue_id, > > > - ch_id, ev); > > > + ch_id, &conf->ev); > > > if (ret) { > > > DPAA_EVENTDEV_ERR( > > > "dpaa_sec_eventq_attach failed: ret: %d\n", ret); diff - > -git > > > a/drivers/event/dpaa2/dpaa2_eventdev.c > > > b/drivers/event/dpaa2/dpaa2_eventdev.c > > > index ffc7b8b073..0137736794 100644 > > > --- a/drivers/event/dpaa2/dpaa2_eventdev.c > > > +++ b/drivers/event/dpaa2/dpaa2_eventdev.c > > > @@ -26,6 +26,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include #include > > > > > > > > > @@ -865,10 +866,10 @@ static int > > > dpaa2_eventdev_crypto_queue_add(const struct rte_eventdev *dev, > > > const struct rte_cryptodev *cryptodev, > > > int32_t rx_queue_id, > > > - const struct rte_event *ev) > > > + const struct rte_event_crypto_adapter_queue_conf *conf) > > > { > > > struct dpaa2_eventdev *priv =3D dev->data->dev_private; > > > - uint8_t ev_qid =3D ev->queue_id; > > > + uint8_t ev_qid =3D conf->ev.queue_id; > > > struct dpaa2_dpcon_dev *dpcon =3D priv->evq_info[ev_qid].dpcon; > > > int ret; > > > > > > @@ -876,10 +877,10 @@ dpaa2_eventdev_crypto_queue_add(const struct > > > rte_eventdev *dev, > > > > > > if (rx_queue_id =3D=3D -1) > > > return dpaa2_eventdev_crypto_queue_add_all(dev, > > > - cryptodev, ev); > > > + cryptodev, &conf->ev); > > > > > > ret =3D dpaa2_sec_eventq_attach(cryptodev, rx_queue_id, > > > - dpcon, ev); > > > + dpcon, &conf->ev); > > > if (ret) { > > > DPAA2_EVENTDEV_ERR( > > > "dpaa2_sec_eventq_attach failed: ret: %d\n", ret); diff > --git > > > a/drivers/event/octeontx/ssovf_evdev.c > > > b/drivers/event/octeontx/ssovf_evdev.c > > > index 9e14e35d10..17acd8ef64 100644 > > > --- a/drivers/event/octeontx/ssovf_evdev.c > > > +++ b/drivers/event/octeontx/ssovf_evdev.c > > > @@ -745,12 +745,12 @@ static int > > > ssovf_crypto_adapter_qp_add(const struct rte_eventdev *dev, > > > const struct rte_cryptodev *cdev, > > > int32_t queue_pair_id, > > > - const struct rte_event *event) > > > + const struct rte_event_crypto_adapter_queue_conf > > > *conf) > > > { > > > struct cpt_instance *qp; > > > uint8_t qp_id; > > > > > > - RTE_SET_USED(event); > > > + RTE_SET_USED(conf); > > > > > > if (queue_pair_id =3D=3D -1) { > > > for (qp_id =3D 0; qp_id < cdev->data->nb_queue_pairs; qp_id++) { > > > diff --git a/lib/eventdev/eventdev_pmd.h > > > b/lib/eventdev/eventdev_pmd.h index 69402668d8..bcfc9cbcb2 100644 > > > --- a/lib/eventdev/eventdev_pmd.h > > > +++ b/lib/eventdev/eventdev_pmd.h > > > @@ -907,6 +907,7 @@ rte_event_pmd_selftest_seqn(struct rte_mbuf > > > *mbuf) } > > > > > > struct rte_cryptodev; > > > +struct rte_event_crypto_adapter_queue_conf; > > > > > > /** > > > * This API may change without prior notice @@ -961,11 +962,11 @@ > > > typedef int (*eventdev_crypto_adapter_caps_get_t) > > > * - <0: Error code returned by the driver function. > > > * > > > */ > > > -typedef int (*eventdev_crypto_adapter_queue_pair_add_t) > > > - (const struct rte_eventdev *dev, > > > - const struct rte_cryptodev *cdev, > > > - int32_t queue_pair_id, > > > - const struct rte_event *event); > > > +typedef int (*eventdev_crypto_adapter_queue_pair_add_t)( > > > + const struct rte_eventdev *dev, > > > + const struct rte_cryptodev *cdev, > > > + int32_t queue_pair_id, > > > + const struct rte_event_crypto_adapter_queue_conf > > > *queue_conf); > > > > > > > > > /** > > > @@ -1074,6 +1075,27 @@ typedef int > > > (*eventdev_crypto_adapter_stats_reset) > > > (const struct rte_eventdev *dev, > > > const struct rte_cryptodev *cdev); > > > > > > +struct rte_event_crypto_adapter_vector_limits; > > > +/** > > > + * Get event vector limits for a given event, crypto device pair. > > > + * > > > + * @param dev > > > + * Event device pointer > > > + * > > > + * @param cdev > > > + * Crypto device pointer > > > + * > > > + * @param[out] limits > > > + * Pointer to the limits structure to be filled. > > > + * > > > + * @return > > > + * - 0: Success. > > > + * - <0: Error code returned by the driver function. > > > + */ > > > +typedef int (*eventdev_crypto_adapter_vector_limits_get_t)( > > > + const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, > > > + struct rte_event_crypto_adapter_vector_limits *limits); > > > + > > > /** > > > * Retrieve the event device's eth Tx adapter capabilities. > > > * > > > @@ -1339,6 +1361,9 @@ struct eventdev_ops { > > > /**< Get crypto stats */ > > > eventdev_crypto_adapter_stats_reset crypto_adapter_stats_reset; > > > /**< Reset crypto stats */ > > > + eventdev_crypto_adapter_vector_limits_get_t > > > + crypto_adapter_vector_limits_get; > > > + /**< Get event vector limits for the crypto adapter */ > > > > > > eventdev_eth_rx_adapter_q_stats_get > > > eth_rx_adapter_queue_stats_get; > > > /**< Get ethernet Rx queue stats */ diff --git > > > a/lib/eventdev/eventdev_trace.h b/lib/eventdev/eventdev_trace.h > > > index 5ec43d80ee..d48cd58850 100644 > > > --- a/lib/eventdev/eventdev_trace.h > > > +++ b/lib/eventdev/eventdev_trace.h > > > @@ -18,6 +18,7 @@ extern "C" { > > > #include > > > > > > #include "rte_eventdev.h" > > > +#include "rte_event_crypto_adapter.h" > > > #include "rte_event_eth_rx_adapter.h" > > > #include "rte_event_timer_adapter.h" > > > > > > @@ -271,11 +272,12 @@ RTE_TRACE_POINT( RTE_TRACE_POINT( > > > rte_eventdev_trace_crypto_adapter_queue_pair_add, > > > RTE_TRACE_POINT_ARGS(uint8_t adptr_id, uint8_t cdev_id, > > > - const void *event, int32_t queue_pair_id), > > > + int32_t queue_pair_id, > > > + const struct rte_event_crypto_adapter_queue_conf *conf), > > > rte_trace_point_emit_u8(adptr_id); > > > rte_trace_point_emit_u8(cdev_id); > > > rte_trace_point_emit_i32(queue_pair_id); > > > - rte_trace_point_emit_ptr(event); > > > + rte_trace_point_emit_ptr(conf); > > > ) > > > > > > RTE_TRACE_POINT( > > > diff --git a/lib/eventdev/rte_event_crypto_adapter.c > > > b/lib/eventdev/rte_event_crypto_adapter.c > > > index 7c695176f4..73a4f231e2 100644 > > > --- a/lib/eventdev/rte_event_crypto_adapter.c > > > +++ b/lib/eventdev/rte_event_crypto_adapter.c > > > @@ -921,11 +921,12 @@ int > > > rte_event_crypto_adapter_queue_pair_add(uint8_t id, > > > uint8_t cdev_id, > > > int32_t queue_pair_id, > > > - const struct rte_event *event) > > > + const struct rte_event_crypto_adapter_queue_conf > > > *conf) > > > { > > > + struct rte_event_crypto_adapter_vector_limits limits; > > > struct event_crypto_adapter *adapter; > > > - struct rte_eventdev *dev; > > > struct crypto_device_info *dev_info; > > > + struct rte_eventdev *dev; > > > uint32_t cap; > > > int ret; > > > > > > @@ -951,11 +952,47 @@ > > > rte_event_crypto_adapter_queue_pair_add(uint8_t > > > id, > > > } > > > > > > if ((cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND) && > > > - (event =3D=3D NULL)) { > > > + (conf =3D=3D NULL)) { > > > RTE_EDEV_LOG_ERR("Conf value can not be NULL for > dev_id=3D%u", > > > cdev_id); > > > return -EINVAL; > > > } > > Newline? > > > Ack >=20 > > > + if ((conf !=3D NULL) && > > Checking conf twice? > Will rewrite as if conf =3D=3D NULL/else, to avoid double checking. >=20 > > > + (conf->flags & RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR)) { > > Else condition if the flags is not set? > There's no additional handing for case when flag is no set. >=20 > > > + if ((cap & > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR) =3D=3D 0) { > > > + RTE_EDEV_LOG_ERR("Event vectorization is not > > > supported," > > > + "dev %" PRIu8 " cdev %" PRIu8, id, > > > + cdev_id); > > > + return -ENOTSUP; > > > + } > > > + > > > + ret =3D rte_event_crypto_adapter_vector_limits_get( > > > + adapter->eventdev_id, cdev_id, &limits); > > > + if (ret < 0) { > > > + RTE_EDEV_LOG_ERR("Failed to get event device vector > > > " > > > + "limits, dev %" PRIu8 " cdev %" PRIu8, > > > + id, cdev_id); > > > + return -EINVAL; > > > + } > > New line? Please check other cases. > > > Ack >=20 > > > + if (conf->vector_sz < limits.min_sz || > > > + conf->vector_sz > limits.max_sz || > > > + conf->vector_timeout_ns < limits.min_timeout_ns || > > > + conf->vector_timeout_ns > limits.max_timeout_ns || > > > + conf->vector_mp =3D=3D NULL) { > > > + RTE_EDEV_LOG_ERR("Invalid event vector > > > configuration," > > > + " dev %" PRIu8 " cdev %" PRIu8, > > > + id, cdev_id); > > > + return -EINVAL; > > > + } > > > + if (conf->vector_mp->elt_size < > > > + (sizeof(struct rte_event_vector) + > > > + (sizeof(uintptr_t) * conf->vector_sz))) { > > > + RTE_EDEV_LOG_ERR("Invalid event vector > > > configuration," > > > + " dev %" PRIu8 " cdev %" PRIu8, > > > + id, cdev_id); > > > + return -EINVAL; > > > + } > > > + } > > > > > > dev_info =3D &adapter->cdevs[cdev_id]; > > > > > > @@ -990,7 +1027,7 @@ > rte_event_crypto_adapter_queue_pair_add(uint8_t > > > id, > > > ret =3D (*dev->dev_ops->crypto_adapter_queue_pair_add)(dev, > > > dev_info->dev, > > > queue_pair_id, > > > - event); > > > + conf); > > > if (ret) > > > return ret; > > > > > > @@ -1030,8 +1067,8 @@ > > > rte_event_crypto_adapter_queue_pair_add(uint8_t > > > id, > > > rte_service_component_runstate_set(adapter->service_id, 1); > > > } > > > > > > - rte_eventdev_trace_crypto_adapter_queue_pair_add(id, cdev_id, > > > event, > > > - queue_pair_id); > > > + rte_eventdev_trace_crypto_adapter_queue_pair_add(id, cdev_id, > > > + queue_pair_id, conf); > > > return 0; > > > } > > > > > > @@ -1290,3 +1327,44 @@ > > > rte_event_crypto_adapter_event_port_get(uint8_t > > > id, uint8_t *event_port_id) > > > > > > return 0; > > > } > > > + > > > +int > > > +rte_event_crypto_adapter_vector_limits_get( > > > + uint8_t dev_id, uint16_t cdev_id, > > > + struct rte_event_crypto_adapter_vector_limits *limits) { > > > + struct rte_cryptodev *cdev; > > > + struct rte_eventdev *dev; > > > + uint32_t cap; > > > + int ret; > > > + > > > + RTE_EVENTDEV_VALID_DEVID_OR_ERR_RET(dev_id, -EINVAL); > > > + > > > + if (!rte_cryptodev_is_valid_dev(cdev_id)) { > > > + RTE_EDEV_LOG_ERR("Invalid dev_id=3D%" PRIu8, cdev_id); > > > + return -EINVAL; > > > + } > > > + > > > + if (limits =3D=3D NULL) > > > + return -EINVAL; > > Add appropriate error message like above? > Ack, will add. >=20 > > > + > > > + dev =3D &rte_eventdevs[dev_id]; > > > + cdev =3D rte_cryptodev_pmd_get_dev(cdev_id); > > > + > > > + ret =3D rte_event_crypto_adapter_caps_get(dev_id, cdev_id, &cap); > > > + if (ret) { > > > + RTE_EDEV_LOG_ERR("Failed to get adapter caps edev %" PRIu8 > > > + "cdev %" PRIu16, dev_id, cdev_id); > > > + return ret; > > > + } > > > + > > > + if (!(cap & RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR)) > > > + return -ENOTSUP; > > Same here. > Ack, will add. >=20 > > > + > > > + RTE_FUNC_PTR_OR_ERR_RET( > > > + *dev->dev_ops->crypto_adapter_vector_limits_get, > > > + -ENOTSUP); > > > + > > > + return dev->dev_ops->crypto_adapter_vector_limits_get( > > > + dev, cdev, limits); > > > +} > > > diff --git a/lib/eventdev/rte_event_crypto_adapter.h > > > b/lib/eventdev/rte_event_crypto_adapter.h > > > index d90a19e72c..7dd6171b9b 100644 > > > --- a/lib/eventdev/rte_event_crypto_adapter.h > > > +++ b/lib/eventdev/rte_event_crypto_adapter.h > > > @@ -253,6 +253,78 @@ struct rte_event_crypto_adapter_conf { > > > */ > > > }; > > > > > > +#define RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR 0x1 > > > +/**< This flag indicates that crypto operations processed on the > > > +crypto > > > + * adapter need to be vectorized > > > + * @see rte_event_crypto_adapter_queue_conf::flags > > > + */ > > > + > > > +/** > > > + * Adapter queue configuration structure */ struct > > > +rte_event_crypto_adapter_queue_conf { > > > + uint32_t flags; > > > + /**< Flags for handling crypto operations > > > + * @see RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR > > > + */ > > > + struct rte_event ev; > > > + /**< If HW supports cryptodev queue pair to event queue binding, > > > + * application is expected to fill in event information. > > > + * @see > > > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND > > > + */ > > > + uint16_t vector_sz; > > > + /**< Indicates the maximum number for crypto operations to combine > > > and > > > + * form a vector. > > > + * @see rte_event_crypto_adapter_vector_limits::min_sz > > > + * @see rte_event_crypto_adapter_vector_limits::max_sz > > > + * Valid when RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR flag is > > > set in > > > + * @see rte_event_crypto_adapter_queue_conf::rx_queue_flags > > rx_queue_flags?? > Typo, should be conf::flags. >=20 > > > + */ > > > + uint64_t vector_timeout_ns; > > > + /**< > > > + * Indicates the maximum number of nanoseconds to wait for > > > aggregating > > > + * crypto operations. Should be within vectorization limits of the > > > + * adapter > > > + * @see rte_event_crypto_adapter_vector_limits::min_timeout_ns > > > + * @see rte_event_crypto_adapter_vector_limits::max_timeout_ns > > > + * Valid when RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR flag is > > > set in > > > + * @see rte_event_crypto_adapter_queue_conf::flags > > > + */ > > > + struct rte_mempool *vector_mp; > > > + /**< Indicates the mempool that should be used for allocating > > > + * rte_event_vector container. > > > + * Should be created by using `rte_event_vector_pool_create`. > > > + * Valid when RTE_EVENT_CRYPTO_ADAPTER_EVENT_VECTOR flag is > > > set in > > > + * @see rte_event_crypto_adapter_queue_conf::flags. > > > + */ > > > +}; > > > + > > > +/** > > > + * A structure used to retrieve event crypto adapter vector limits. > > > + */ > > > +struct rte_event_crypto_adapter_vector_limits { > > > + uint16_t min_sz; > > > + /**< Minimum vector limit configurable. > > > + * @see rte_event_crypto_adapter_queue_conf::vector_sz > > > + */ > > > + uint16_t max_sz; > > > + /**< Maximum vector limit configurable. > > > + * @see rte_event_crypto_adapter_queue_conf::vector_sz > > > + */ > > > + uint8_t log2_sz; > > > + /**< True if the size configured should be in log2. > > > + * @see rte_event_crypto_adapter_queue_conf::vector_sz > > > + */ > > > + uint64_t min_timeout_ns; > > > + /**< Minimum vector timeout configurable. > > > + * @see rte_event_crypto_adapter_queue_conf::vector_timeout_ns > > > + */ > > > + uint64_t max_timeout_ns; > > > + /**< Maximum vector timeout configurable. > > > + * @see rte_event_crypto_adapter_queue_conf::vector_timeout_ns > > > + */ > > > +}; > > > + > > > /** > > > * Function type used for adapter configuration callback. The callba= ck is > > > * used to fill in members of the struct > > > rte_event_crypto_adapter_conf, this @@ -392,10 +464,9 @@ > > rte_event_crypto_adapter_free(uint8_t id); > > > * Cryptodev queue pair identifier. If queue_pair_id is set -1, > > > * adapter adds all the pre configured queue pairs to the instance. > > > * > > > - * @param event > > > - * if HW supports cryptodev queue pair to event queue binding, > > > application is > > > - * expected to fill in event information, else it will be NULL. > > > - * @see > RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND > > > + * @param conf > > > + * Additional configuration structure of type > > > + * *rte_event_crypto_adapter_queue_conf* > > > * > > > * @return > > > * - 0: Success, queue pair added correctly. > > > @@ -405,7 +476,7 @@ int > > > rte_event_crypto_adapter_queue_pair_add(uint8_t id, > > > uint8_t cdev_id, > > > int32_t queue_pair_id, > > > - const struct rte_event *event); > > > + const struct rte_event_crypto_adapter_queue_conf > > > *conf); > > > > > > /** > > > * Delete a queue pair from an event crypto adapter. > > > @@ -523,6 +594,26 @@ rte_event_crypto_adapter_service_id_get(uint8_t > > > id, uint32_t *service_id); int > > > rte_event_crypto_adapter_event_port_get(uint8_t > > > id, uint8_t *event_port_id); > > > > > > +/** > > > + * Retrieve vector limits for a given event dev and crypto dev pair. > > > + * @see rte_event_crypto_adapter_vector_limits > > > + * > > > + * @param dev_id > > > + * Event device identifier. > > > + * @param cdev_id > > > + * Crypto device identifier. > > > + * @param [out] limits > > > + * A pointer to rte_event_crypto_adapter_vector_limits structure > > > +that has to > > > + * be filled. > > Space missing before "be filled" > Ack >=20 > > > + * > > > + * @return > > > + * - 0: Success. > > > + * - <0: Error code on failure. > > > + */ > > > +int rte_event_crypto_adapter_vector_limits_get( > > > + uint8_t dev_id, uint16_t cdev_id, > > > + struct rte_event_crypto_adapter_vector_limits *limits); > > > + > > > /** > > > * Enqueue a burst of crypto operations as event objects supplied > > > in > > > *rte_event* > > > * structure on an event crypto adapter designated by its event > > > *dev_id* through diff --git > > > a/lib/eventdev/rte_event_eth_rx_adapter.h > > > b/lib/eventdev/rte_event_eth_rx_adapter.h > > > index 3608a7b2cf..c8f2936866 100644 > > > --- a/lib/eventdev/rte_event_eth_rx_adapter.h > > > +++ b/lib/eventdev/rte_event_eth_rx_adapter.h > > > @@ -457,7 +457,8 @@ int rte_event_eth_rx_adapter_free(uint8_t id); > > > * @see RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ > > > * > > > * @param conf > > > - * Additional configuration structure of type > > > *rte_event_eth_rx_adapter_conf* > > > + * Additional configuration structure of type > > > + * *rte_event_eth_rx_adapter_queue_conf* > > These changes are not relevant. Please consider sending separate patch. > > > Ack, Will send this change as a separate patch. >=20 > > > * > > > * @return > > > * - 0: Success, Receive queue added correctly. > > > diff --git a/lib/eventdev/rte_eventdev.h > > > b/lib/eventdev/rte_eventdev.h index > > > 6a6f6ea4c1..1a737bf851 100644 > > > --- a/lib/eventdev/rte_eventdev.h > > > +++ b/lib/eventdev/rte_eventdev.h > > > @@ -1203,6 +1203,9 @@ struct rte_event_vector { > > > #define RTE_EVENT_TYPE_ETH_RX_ADAPTER_VECTOR > \ > > > (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_ETH_RX_ADAPTER) > /**< The > > > event vector generated from eth Rx adapter. */ > > > +#define RTE_EVENT_TYPE_CRYPTODEV_VECTOR = \ > > > + (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_CRYPTODEV) /**< The > > > event > > > +vector generated from cryptodev adapter. */ > > > > > > #define RTE_EVENT_TYPE_MAX 0x10 > > > /**< Maximum number of event types */ @@ -1420,6 +1423,11 @@ > > > rte_event_timer_adapter_caps_get(uint8_t dev_id, uint32_t *caps); > > > * the private data information along with the crypto session. > > > */ > > > > > > +#define RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR 0x10 > > > +/**< Flag indicates HW is capable of aggregating processed > > > + * crypto operations into rte_event_vector. > > > + */ > > > + > > > /** > > > * Retrieve the event device's crypto adapter capabilities for the > > > * specified cryptodev device > > > -- > > > 2.25.1