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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5877.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1c6dcb91-6bd4-4081-8e12-08db5c358750 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 May 2023 09:01:57.5751 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Vv8wRRC/reNEyjSUUw5xl9D0RmW39HLNEwKmp5KshVWlZQ4I9CsIqyEuZkLpK2Ll3llFyOcT7ExPsjFh5N/VcQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR11MB7589 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > +cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf) { > + struct cpfl_vport *cpfl_vport =3D > + (struct cpfl_vport *)dev->data->dev_private; > + > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter_base =3D vport->adapter; > + uint16_t logic_qid =3D cpfl_vport->nb_p2p_txq; > + struct cpfl_txq_hairpin_info *hairpin_info; > + struct idpf_hw *hw =3D &adapter_base->hw; > + struct cpfl_tx_queue *cpfl_txq; > + struct idpf_tx_queue *txq, *cq; > + const struct rte_memzone *mz; > + uint32_t ring_size; > + uint16_t peer_port, peer_q; > + > + if (vport->txq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > + PMD_INIT_LOG(ERR, "Only spilt queue model supports hairpin > queue."); > + return -EINVAL; > + } > + > + if (conf->peer_count !=3D 1) { > + PMD_INIT_LOG(ERR, "Can't support Tx hairpin queue peer > count %d", conf->peer_count); > + return -EINVAL; > + } > + > + peer_port =3D conf->peers[0].port; > + peer_q =3D conf->peers[0].queue; > + > + if (nb_desc % CPFL_ALIGN_RING_DESC !=3D 0 || > + nb_desc > CPFL_MAX_RING_DESC || > + nb_desc < CPFL_MIN_RING_DESC) { > + PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is > invalid", > + nb_desc); > + return -EINVAL; > + } > + > + /* Free memory if needed. */ > + if (dev->data->tx_queues[queue_idx]) { > + cpfl_tx_queue_release(dev->data->tx_queues[queue_idx]); > + dev->data->tx_queues[queue_idx] =3D NULL; > + } > + > + /* Allocate the TX queue data structure. */ > + cpfl_txq =3D rte_zmalloc_socket("cpfl hairpin txq", > + sizeof(struct cpfl_tx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!cpfl_txq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx queue > structure"); > + return -ENOMEM; > + } > + > + txq =3D &cpfl_txq->base; > + hairpin_info =3D &cpfl_txq->hairpin_info; > + /* Txq ring length should be 2 times of Tx completion queue size. */ > + txq->nb_tx_desc =3D nb_desc * 2; > + txq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info.tx_start_qid, logic_qid); > + txq->port_id =3D dev->data->port_id; > + hairpin_info->hairpin_q =3D true; > + hairpin_info->peer_rxp =3D peer_port; > + hairpin_info->peer_rxq_id =3D peer_q; > + > + if (conf->manual_bind !=3D 0) > + cpfl_vport->p2p_manual_bind =3D true; > + else > + cpfl_vport->p2p_manual_bind =3D false; > + > + /* Always Tx hairpin queue allocates Tx HW ring */ > + ring_size =3D RTE_ALIGN(txq->nb_tx_desc * CPFL_P2P_DESC_LEN, > + CPFL_DMA_MEM_ALIGN); > + mz =3D rte_eth_dma_zone_reserve(dev, "hairpin_tx_ring", logic_qid, > + ring_size + CPFL_P2P_RING_BUF, > + CPFL_RING_BASE_ALIGN, > + dev->device->numa_node); > + if (!mz) { > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX"); > + rte_free(txq->sw_ring); > + rte_free(txq); > + return -ENOMEM; > + } > + > + txq->tx_ring_phys_addr =3D mz->iova; > + txq->desc_ring =3D mz->addr; > + txq->mz =3D mz; > + > + cpfl_tx_hairpin_descq_reset(txq); > + txq->qtx_tail =3D hw->hw_addr + > + cpfl_hw_qtail_get(cpfl_vport- > >p2p_q_chunks_info.tx_qtail_start, > + logic_qid, cpfl_vport- > >p2p_q_chunks_info.tx_qtail_spacing); > + txq->ops =3D &def_txq_ops; > + > + if (cpfl_vport->p2p_tx_complq =3D=3D NULL) { [Liu, Mingxia] In cpfl_rx_hairpin_queue_setup(), "logic_qid" is used to ide= ntify if it is the first time to allocate "p2p_rx_bufq" buffer,=20 Can it be unified, using logic_qid =3D=3D 0 or p2p_tx_complq/ p2p_rx_bufq = =3D=3D NULL ? > -----Original Message----- > From: Xing, Beilei > Sent: Friday, May 19, 2023 3:31 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Liu, Mingxia ; Xing, Beilei > ; Wang, Xiao W > Subject: [PATCH v3 05/10] net/cpfl: support hairpin queue setup and relea= se >=20 > From: Beilei Xing >=20 > Support hairpin Rx/Tx queue setup and release. >=20 > Signed-off-by: Xiao Wang > Signed-off-by: Mingxia Liu > Signed-off-by: Beilei Xing > --- > drivers/net/cpfl/cpfl_ethdev.c | 6 + > drivers/net/cpfl/cpfl_ethdev.h | 12 + > drivers/net/cpfl/cpfl_rxtx.c | 373 +++++++++++++++++++++++- > drivers/net/cpfl/cpfl_rxtx.h | 26 ++ > drivers/net/cpfl/cpfl_rxtx_vec_common.h | 4 + > 5 files changed, 420 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethde= v.c index > 8e471d2a9b..03813716ce 100644 > --- a/drivers/net/cpfl/cpfl_ethdev.c > +++ b/drivers/net/cpfl/cpfl_ethdev.c > @@ -874,6 +874,10 @@ cpfl_dev_close(struct rte_eth_dev *dev) > struct cpfl_adapter_ext *adapter =3D CPFL_ADAPTER_TO_EXT(vport- > >adapter); >=20 > cpfl_dev_stop(dev); > + if (cpfl_vport->p2p_mp) { > + rte_mempool_free(cpfl_vport->p2p_mp); > + cpfl_vport->p2p_mp =3D NULL; > + } >=20 > if (!adapter->base.is_rx_singleq && !adapter->base.is_tx_singleq) > cpfl_p2p_queue_grps_del(vport); > @@ -916,6 +920,8 @@ static const struct eth_dev_ops cpfl_eth_dev_ops =3D = { > .xstats_get_names =3D cpfl_dev_xstats_get_names, > .xstats_reset =3D cpfl_dev_xstats_reset, > .hairpin_cap_get =3D cpfl_hairpin_cap_get, > + .rx_hairpin_queue_setup =3D cpfl_rx_hairpin_queue_setup, > + .tx_hairpin_queue_setup =3D cpfl_tx_hairpin_queue_setup, > }; >=20 > static int > diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethde= v.h index > 65c9a195b2..a48344299c 100644 > --- a/drivers/net/cpfl/cpfl_ethdev.h > +++ b/drivers/net/cpfl/cpfl_ethdev.h > @@ -89,6 +89,18 @@ struct p2p_queue_chunks_info { struct cpfl_vport { > struct idpf_vport base; > struct p2p_queue_chunks_info p2p_q_chunks_info; > + > + struct rte_mempool *p2p_mp; > + > + uint16_t nb_data_rxq; > + uint16_t nb_data_txq; > + uint16_t nb_p2p_rxq; > + uint16_t nb_p2p_txq; > + > + struct idpf_rx_queue *p2p_rx_bufq; > + struct idpf_tx_queue *p2p_tx_complq; > + bool p2p_manual_bind; > + > }; >=20 > struct cpfl_adapter_ext { > diff --git a/drivers/net/cpfl/cpfl_rxtx.c b/drivers/net/cpfl/cpfl_rxtx.c = index > 04a51b8d15..333a399e73 100644 > --- a/drivers/net/cpfl/cpfl_rxtx.c > +++ b/drivers/net/cpfl/cpfl_rxtx.c > @@ -10,6 +10,79 @@ > #include "cpfl_rxtx.h" > #include "cpfl_rxtx_vec_common.h" >=20 > +uint16_t > +cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset) { > + return start_qid + offset; > +} > + > +uint64_t > +cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t > +tail_spacing) { > + return tail_start + offset * tail_spacing; } > + > +static inline void > +cpfl_tx_hairpin_descq_reset(struct idpf_tx_queue *txq) { > + uint32_t i, size; > + > + if (!txq) { > + PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL"); > + return; > + } > + > + size =3D txq->nb_tx_desc * CPFL_P2P_DESC_LEN; > + for (i =3D 0; i < size; i++) > + ((volatile char *)txq->desc_ring)[i] =3D 0; } > + > +static inline void > +cpfl_tx_hairpin_complq_reset(struct idpf_tx_queue *cq) { > + uint32_t i, size; > + > + if (!cq) { > + PMD_DRV_LOG(DEBUG, "Pointer to complq is NULL"); > + return; > + } > + > + size =3D cq->nb_tx_desc * CPFL_P2P_DESC_LEN; > + for (i =3D 0; i < size; i++) > + ((volatile char *)cq->compl_ring)[i] =3D 0; } > + > +static inline void > +cpfl_rx_hairpin_descq_reset(struct idpf_rx_queue *rxq) { > + uint16_t len; > + uint32_t i; > + > + if (!rxq) > + return; > + > + len =3D rxq->nb_rx_desc; > + for (i =3D 0; i < len * CPFL_P2P_DESC_LEN; i++) > + ((volatile char *)rxq->rx_ring)[i] =3D 0; } > + > +static inline void > +cpfl_rx_hairpin_bufq_reset(struct idpf_rx_queue *rxbq) { > + uint16_t len; > + uint32_t i; > + > + if (!rxbq) > + return; > + > + len =3D rxbq->nb_rx_desc; > + for (i =3D 0; i < len * CPFL_P2P_DESC_LEN; i++) > + ((volatile char *)rxbq->rx_ring)[i] =3D 0; > + > + rxbq->bufq1 =3D NULL; > + rxbq->bufq2 =3D NULL; > +} > + > static uint64_t > cpfl_rx_offload_convert(uint64_t offload) { @@ -234,7 +307,10 @@ > cpfl_rx_queue_release(void *rxq) >=20 > /* Split queue */ > if (!q->adapter->is_rx_singleq) { > - if (q->bufq2) > + /* the mz is shared between Tx/Rx hairpin, let Rx_release > + * free the buf, q->bufq1->mz and q->mz. > + */ > + if (!cpfl_rxq->hairpin_info.hairpin_q && q->bufq2) > cpfl_rx_split_bufq_release(q->bufq2); >=20 > if (q->bufq1) > @@ -385,6 +461,7 @@ cpfl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t > queue_idx, > } > } >=20 > + cpfl_vport->nb_data_rxq++; > rxq->q_set =3D true; > dev->data->rx_queues[queue_idx] =3D cpfl_rxq; >=20 > @@ -548,6 +625,7 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t > queue_idx, > txq->qtx_tail =3D hw->hw_addr + (vport->chunks_info.tx_qtail_start + > queue_idx * vport->chunks_info.tx_qtail_spacing); > txq->ops =3D &def_txq_ops; > + cpfl_vport->nb_data_txq++; > txq->q_set =3D true; > dev->data->tx_queues[queue_idx] =3D cpfl_txq; >=20 > @@ -562,6 +640,297 @@ cpfl_tx_queue_setup(struct rte_eth_dev *dev, > uint16_t queue_idx, > return ret; > } >=20 > +static int > +cpfl_rx_hairpin_bufq_setup(struct rte_eth_dev *dev, struct idpf_rx_queue > *bufq, > + uint16_t logic_qid, uint16_t nb_desc) { > + struct cpfl_vport *cpfl_vport =3D > + (struct cpfl_vport *)dev->data->dev_private; > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter =3D vport->adapter; > + struct rte_mempool *mp; > + char pool_name[RTE_MEMPOOL_NAMESIZE]; > + > + mp =3D cpfl_vport->p2p_mp; > + if (!mp) { > + snprintf(pool_name, RTE_MEMPOOL_NAMESIZE, > "p2p_mb_pool_%u", > + dev->data->port_id); > + mp =3D rte_pktmbuf_pool_create(pool_name, > CPFL_P2P_NB_MBUF, CPFL_P2P_CACHE_SIZE, > + 0, CPFL_P2P_MBUF_SIZE, dev- > >device->numa_node); > + if (!mp) { > + PMD_INIT_LOG(ERR, "Failed to allocate mbuf pool for > p2p"); > + return -ENOMEM; > + } > + cpfl_vport->p2p_mp =3D mp; > + } > + > + bufq->mp =3D mp; > + bufq->nb_rx_desc =3D nb_desc; > + bufq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info.rx_buf_start_qid, logic_qid); > + bufq->port_id =3D dev->data->port_id; > + bufq->adapter =3D adapter; > + bufq->rx_buf_len =3D CPFL_P2P_MBUF_SIZE - > RTE_PKTMBUF_HEADROOM; > + > + bufq->sw_ring =3D rte_zmalloc("sw ring", > + sizeof(struct rte_mbuf *) * nb_desc, > + RTE_CACHE_LINE_SIZE); > + if (!bufq->sw_ring) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring"); > + return -ENOMEM; > + } > + > + bufq->q_set =3D true; > + bufq->ops =3D &def_rxq_ops; > + > + return 0; > +} > + > +int > +cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf) { > + struct cpfl_vport *cpfl_vport =3D (struct cpfl_vport *)dev->data- > >dev_private; > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter_base =3D vport->adapter; > + uint16_t logic_qid =3D cpfl_vport->nb_p2p_rxq; > + struct cpfl_rxq_hairpin_info *hairpin_info; > + struct cpfl_rx_queue *cpfl_rxq; > + struct idpf_rx_queue *bufq1 =3D NULL; > + struct idpf_rx_queue *rxq; > + uint16_t peer_port, peer_q; > + uint16_t qid; > + int ret; > + > + if (vport->rxq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > + PMD_INIT_LOG(ERR, "Only spilt queue model supports hairpin > queue."); > + return -EINVAL; > + } > + > + if (conf->peer_count !=3D 1) { > + PMD_INIT_LOG(ERR, "Can't support Rx hairpin queue peer > count %d", conf->peer_count); > + return -EINVAL; > + } > + > + peer_port =3D conf->peers[0].port; > + peer_q =3D conf->peers[0].queue; > + > + if (nb_desc % CPFL_ALIGN_RING_DESC !=3D 0 || > + nb_desc > CPFL_MAX_RING_DESC || > + nb_desc < CPFL_MIN_RING_DESC) { > + PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is > invalid", nb_desc); > + return -EINVAL; > + } > + > + /* Free memory if needed */ > + if (dev->data->rx_queues[queue_idx]) { > + cpfl_rx_queue_release(dev->data->rx_queues[queue_idx]); > + dev->data->rx_queues[queue_idx] =3D NULL; > + } > + > + /* Setup Rx description queue */ > + cpfl_rxq =3D rte_zmalloc_socket("cpfl hairpin rxq", > + sizeof(struct cpfl_rx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!cpfl_rxq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for rx queue > data structure"); > + return -ENOMEM; > + } > + > + rxq =3D &cpfl_rxq->base; > + hairpin_info =3D &cpfl_rxq->hairpin_info; > + rxq->nb_rx_desc =3D nb_desc * 2; > + rxq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info.rx_start_qid, logic_qid); > + rxq->port_id =3D dev->data->port_id; > + rxq->adapter =3D adapter_base; > + rxq->rx_buf_len =3D CPFL_P2P_MBUF_SIZE - RTE_PKTMBUF_HEADROOM; > + hairpin_info->hairpin_q =3D true; > + hairpin_info->peer_txp =3D peer_port; > + hairpin_info->peer_txq_id =3D peer_q; > + > + if (conf->manual_bind !=3D 0) > + cpfl_vport->p2p_manual_bind =3D true; > + else > + cpfl_vport->p2p_manual_bind =3D false; > + > + /* setup 1 Rx buffer queue for the 1st hairpin rxq */ > + if (logic_qid =3D=3D 0) { > + bufq1 =3D rte_zmalloc_socket("hairpin rx bufq1", > + sizeof(struct idpf_rx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!bufq1) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for > hairpin Rx buffer queue 1."); > + ret =3D -ENOMEM; > + goto err_alloc_bufq1; > + } > + qid =3D 2 * logic_qid; > + ret =3D cpfl_rx_hairpin_bufq_setup(dev, bufq1, qid, nb_desc); > + if (ret) { > + PMD_INIT_LOG(ERR, "Failed to setup hairpin Rx buffer > queue 1"); > + ret =3D -EINVAL; > + goto err_setup_bufq1; > + } > + cpfl_vport->p2p_rx_bufq =3D bufq1; > + } > + > + rxq->bufq1 =3D cpfl_vport->p2p_rx_bufq; > + rxq->bufq2 =3D NULL; > + > + cpfl_vport->nb_p2p_rxq++; > + rxq->q_set =3D true; > + dev->data->rx_queues[queue_idx] =3D cpfl_rxq; > + > + return 0; > + > +err_setup_bufq1: > + rte_free(bufq1); > +err_alloc_bufq1: > + rte_free(rxq); > + > + return ret; > +} > + > +int > +cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf) { > + struct cpfl_vport *cpfl_vport =3D > + (struct cpfl_vport *)dev->data->dev_private; > + > + struct idpf_vport *vport =3D &cpfl_vport->base; > + struct idpf_adapter *adapter_base =3D vport->adapter; > + uint16_t logic_qid =3D cpfl_vport->nb_p2p_txq; > + struct cpfl_txq_hairpin_info *hairpin_info; > + struct idpf_hw *hw =3D &adapter_base->hw; > + struct cpfl_tx_queue *cpfl_txq; > + struct idpf_tx_queue *txq, *cq; > + const struct rte_memzone *mz; > + uint32_t ring_size; > + uint16_t peer_port, peer_q; > + > + if (vport->txq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SINGLE) { > + PMD_INIT_LOG(ERR, "Only spilt queue model supports hairpin > queue."); > + return -EINVAL; > + } > + > + if (conf->peer_count !=3D 1) { > + PMD_INIT_LOG(ERR, "Can't support Tx hairpin queue peer > count %d", conf->peer_count); > + return -EINVAL; > + } > + > + peer_port =3D conf->peers[0].port; > + peer_q =3D conf->peers[0].queue; > + > + if (nb_desc % CPFL_ALIGN_RING_DESC !=3D 0 || > + nb_desc > CPFL_MAX_RING_DESC || > + nb_desc < CPFL_MIN_RING_DESC) { > + PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is > invalid", > + nb_desc); > + return -EINVAL; > + } > + > + /* Free memory if needed. */ > + if (dev->data->tx_queues[queue_idx]) { > + cpfl_tx_queue_release(dev->data->tx_queues[queue_idx]); > + dev->data->tx_queues[queue_idx] =3D NULL; > + } > + > + /* Allocate the TX queue data structure. */ > + cpfl_txq =3D rte_zmalloc_socket("cpfl hairpin txq", > + sizeof(struct cpfl_tx_queue), > + RTE_CACHE_LINE_SIZE, > + SOCKET_ID_ANY); > + if (!cpfl_txq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx queue > structure"); > + return -ENOMEM; > + } > + > + txq =3D &cpfl_txq->base; > + hairpin_info =3D &cpfl_txq->hairpin_info; > + /* Txq ring length should be 2 times of Tx completion queue size. */ > + txq->nb_tx_desc =3D nb_desc * 2; > + txq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info.tx_start_qid, logic_qid); > + txq->port_id =3D dev->data->port_id; > + hairpin_info->hairpin_q =3D true; > + hairpin_info->peer_rxp =3D peer_port; > + hairpin_info->peer_rxq_id =3D peer_q; > + > + if (conf->manual_bind !=3D 0) > + cpfl_vport->p2p_manual_bind =3D true; > + else > + cpfl_vport->p2p_manual_bind =3D false; > + > + /* Always Tx hairpin queue allocates Tx HW ring */ > + ring_size =3D RTE_ALIGN(txq->nb_tx_desc * CPFL_P2P_DESC_LEN, > + CPFL_DMA_MEM_ALIGN); > + mz =3D rte_eth_dma_zone_reserve(dev, "hairpin_tx_ring", logic_qid, > + ring_size + CPFL_P2P_RING_BUF, > + CPFL_RING_BASE_ALIGN, > + dev->device->numa_node); > + if (!mz) { > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX"); > + rte_free(txq->sw_ring); > + rte_free(txq); > + return -ENOMEM; > + } > + > + txq->tx_ring_phys_addr =3D mz->iova; > + txq->desc_ring =3D mz->addr; > + txq->mz =3D mz; > + > + cpfl_tx_hairpin_descq_reset(txq); > + txq->qtx_tail =3D hw->hw_addr + > + cpfl_hw_qtail_get(cpfl_vport- > >p2p_q_chunks_info.tx_qtail_start, > + logic_qid, cpfl_vport- > >p2p_q_chunks_info.tx_qtail_spacing); > + txq->ops =3D &def_txq_ops; > + > + if (cpfl_vport->p2p_tx_complq =3D=3D NULL) { [Liu, Mingxia] In cpfl_rx_hairpin_queue_setup(), "logic_qid" is used to ide= ntify if it is the first time to allocate "p2p_rx_bufq" buffer,=20 Can it be unified, using logic_qid =3D=3D 0 or p2p_tx_complq/ p2p_rx_bufq = =3D=3D NULL ? > + cq =3D rte_zmalloc_socket("cpfl hairpin cq", > + sizeof(struct idpf_tx_queue), > + RTE_CACHE_LINE_SIZE, > + dev->device->numa_node); > + if (!cq) { > + PMD_INIT_LOG(ERR, "Failed to allocate memory for tx > queue structure"); > + return -ENOMEM; > + } > + > + cq->nb_tx_desc =3D nb_desc; > + cq->queue_id =3D cpfl_hw_qid_get(cpfl_vport- > >p2p_q_chunks_info.tx_compl_start_qid, 0); > + cq->port_id =3D dev->data->port_id; > + > + /* Tx completion queue always allocates the HW ring */ > + ring_size =3D RTE_ALIGN(cq->nb_tx_desc * CPFL_P2P_DESC_LEN, > + CPFL_DMA_MEM_ALIGN); > + mz =3D rte_eth_dma_zone_reserve(dev, "hairpin_tx_compl_ring", > logic_qid, > + ring_size + CPFL_P2P_RING_BUF, > + CPFL_RING_BASE_ALIGN, > + dev->device->numa_node); > + if (!mz) { > + PMD_INIT_LOG(ERR, "Failed to reserve DMA memory > for TX completion queue"); > + rte_free(txq->sw_ring); > + rte_free(txq); > + return -ENOMEM; > + } > + cq->tx_ring_phys_addr =3D mz->iova; > + cq->compl_ring =3D mz->addr; > + cq->mz =3D mz; > + > + cpfl_tx_hairpin_complq_reset(cq); > + cpfl_vport->p2p_tx_complq =3D cq; > + } > + > + txq->complq =3D cpfl_vport->p2p_tx_complq; > + > + cpfl_vport->nb_p2p_txq++; > + txq->q_set =3D true; > + dev->data->tx_queues[queue_idx] =3D cpfl_txq; > + > + return 0; > +} > + > int > cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) { @@ = - > 865,6 +1234,8 @@ cpfl_set_rx_function(struct rte_eth_dev *dev) > if (vport->rx_vec_allowed) { > for (i =3D 0; i < dev->data->nb_rx_queues; i++) { > cpfl_rxq =3D dev->data->rx_queues[i]; > + if (cpfl_rxq->hairpin_info.hairpin_q) > + continue; > (void)idpf_qc_splitq_rx_vec_setup(&cpfl_rxq- > >base); > } > #ifdef CC_AVX512_SUPPORT > diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h = index > 3a87a1f4b3..5e9f2dada7 100644 > --- a/drivers/net/cpfl/cpfl_rxtx.h > +++ b/drivers/net/cpfl/cpfl_rxtx.h > @@ -13,6 +13,7 @@ > #define CPFL_MIN_RING_DESC 32 > #define CPFL_MAX_RING_DESC 4096 > #define CPFL_DMA_MEM_ALIGN 4096 > +#define CPFL_P2P_DESC_LEN 16 > #define CPFL_MAX_HAIRPINQ_RX_2_TX 1 > #define CPFL_MAX_HAIRPINQ_TX_2_RX 1 > #define CPFL_MAX_HAIRPINQ_NB_DESC 1024 > @@ -21,6 +22,10 @@ > #define CPFL_P2P_NB_TX_COMPLQ 1 > #define CPFL_P2P_NB_QUEUE_GRPS 1 > #define CPFL_P2P_QUEUE_GRP_ID 1 > +#define CPFL_P2P_NB_MBUF 4096 > +#define CPFL_P2P_CACHE_SIZE 250 > +#define CPFL_P2P_MBUF_SIZE 2048 > +#define CPFL_P2P_RING_BUF 128 > /* Base address of the HW descriptor ring should be 128B aligned. */ > #define CPFL_RING_BASE_ALIGN 128 >=20 > @@ -31,12 +36,26 @@ >=20 > #define CPFL_SUPPORT_CHAIN_NUM 5 >=20 > +struct cpfl_rxq_hairpin_info { > + bool hairpin_q; /* if rx queue is a hairpin queue */ > + uint16_t peer_txp; > + uint16_t peer_txq_id; > +}; > + > struct cpfl_rx_queue { > struct idpf_rx_queue base; > + struct cpfl_rxq_hairpin_info hairpin_info; }; > + > +struct cpfl_txq_hairpin_info { > + bool hairpin_q; /* if tx queue is a hairpin queue */ > + uint16_t peer_rxp; > + uint16_t peer_rxq_id; > }; >=20 > struct cpfl_tx_queue { > struct idpf_tx_queue base; > + struct cpfl_txq_hairpin_info hairpin_info; > }; >=20 > int cpfl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, @@ = - > 57,4 +76,11 @@ void cpfl_dev_tx_queue_release(struct rte_eth_dev *dev, > uint16_t qid); void cpfl_dev_rx_queue_release(struct rte_eth_dev *dev, > uint16_t qid); void cpfl_set_rx_function(struct rte_eth_dev *dev); void > cpfl_set_tx_function(struct rte_eth_dev *dev); > +uint16_t cpfl_hw_qid_get(uint16_t start_qid, uint16_t offset); uint64_t > +cpfl_hw_qtail_get(uint64_t tail_start, uint16_t offset, uint64_t > +tail_spacing); int cpfl_rx_hairpin_queue_setup(struct rte_eth_dev *dev, > uint16_t queue_idx, > + uint16_t nb_desc, const struct > rte_eth_hairpin_conf *conf); int > +cpfl_tx_hairpin_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, > + uint16_t nb_desc, > + const struct rte_eth_hairpin_conf *conf); > #endif /* _CPFL_RXTX_H_ */ > diff --git a/drivers/net/cpfl/cpfl_rxtx_vec_common.h > b/drivers/net/cpfl/cpfl_rxtx_vec_common.h > index 5690b17911..d8e9191196 100644 > --- a/drivers/net/cpfl/cpfl_rxtx_vec_common.h > +++ b/drivers/net/cpfl/cpfl_rxtx_vec_common.h > @@ -85,6 +85,8 @@ cpfl_rx_vec_dev_check_default(struct rte_eth_dev *dev) > cpfl_rxq =3D dev->data->rx_queues[i]; > default_ret =3D cpfl_rx_vec_queue_default(&cpfl_rxq->base); > if (vport->rxq_model =3D=3D VIRTCHNL2_QUEUE_MODEL_SPLIT) { > + if (cpfl_rxq->hairpin_info.hairpin_q) > + continue; > splitq_ret =3D cpfl_rx_splitq_vec_default(&cpfl_rxq- > >base); > ret =3D splitq_ret && default_ret; > } else { > @@ -106,6 +108,8 @@ cpfl_tx_vec_dev_check_default(struct rte_eth_dev *dev= ) >=20 > for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > cpfl_txq =3D dev->data->tx_queues[i]; > + if (cpfl_txq->hairpin_info.hairpin_q) > + continue; > ret =3D cpfl_tx_vec_queue_default(&cpfl_txq->base); > if (ret =3D=3D CPFL_SCALAR_PATH) > return CPFL_SCALAR_PATH; > -- > 2.26.2