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Mon, 10 May 2021 17:48:35 +0000 From: Pavan Nikhilesh Bhagavatula To: Honnappa Nagarahalli , "thomas@monjalon.net" CC: Jerin Jacob Kollanukkaran , "juraj.linkes@pantheon.tech" , Jan Viktorin , Ruifeng Wang , Bruce Richardson , "dev@dpdk.org" , nd , nd Thread-Topic: [dpdk-dev] [EXT] Re: [PATCH] config/arm: add ability to express arch extensions Thread-Index: AQHXRcDmsL32CYMdQ0atcuDOTTlhFKrc/LSA Date: Mon, 10 May 2021 17:48:35 +0000 Message-ID: References: <20210505121423.850-1-pbhagavatula@marvell.com> <1699304.vFISr3HHSL@thomas> In-Reply-To: Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=marvell.com; x-originating-ip: [2405:201:d009:304d:a48b:71f6:b5cc:6407] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 550a51d0-d03d-45a3-10e6-08d913dbd5e1 x-ms-traffictypediagnostic: PH0PR18MB3895: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1107; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR18MB4086.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 550a51d0-d03d-45a3-10e6-08d913dbd5e1 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 May 2021 17:48:35.5344 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: y7DwB5hJegF0d1D4YO+cN4OZQmjNN5y4mPmAd13BfDDLlcwl462gd7UwvKkeE6Y1x5bXFPBn5bvUAo9SthNBqoqqxsKp5UO1whstbY6ArZw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR18MB3895 X-Proofpoint-GUID: ZC2Yei5eOCmS0SjDrtQOHvxhhuJQs681 X-Proofpoint-ORIG-GUID: ZC2Yei5eOCmS0SjDrtQOHvxhhuJQs681 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-10_11:2021-05-10, 2021-05-10 signatures=0 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH] config/arm: add ability to express arch extensions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >-----Original Message----- >From: dev On Behalf Of Honnappa >Nagarahalli >Sent: Monday, May 10, 2021 10:51 PM >To: Pavan Nikhilesh Bhagavatula ; >thomas@monjalon.net >Cc: Jerin Jacob Kollanukkaran ; >juraj.linkes@pantheon.tech; Jan Viktorin ; >Ruifeng Wang ; Bruce Richardson >; dev@dpdk.org; nd ; >Honnappa Nagarahalli ; nd > >Subject: Re: [dpdk-dev] [EXT] Re: [PATCH] config/arm: add ability to >express arch extensions > > >> >> >05/05/2021 14:14, pbhagavatula@marvell.com: >> >> From: Pavan Nikhilesh >> >> >> >> The ARM architecture allows SoCs to have extensions in addition to >> >> base profiles such as Large System Extension (LSE), CRC etc. >> >> >> >> Add ability to declare SoC specific extensions. >> >> >> >> Signed-off-by: Pavan Nikhilesh >> > >> >I don't know what it is fixing. It is an optimization? >> >Is it candidate for next release? >> >> Its more of an enhancement, the default n2 march flag doesn't >describe >> anything about the extensions that a specific SoC has. >> In case of OCTEON 10 SoC it has support for LSE and CRC in additional >to the >> basic n2 profile. >> This patch allows SoC to add extensions to the -march flag. >> Default n2 march : -march=3Darmv8.5-a+crypto+sve2 >> OCTEON 10 march : -march=3Darmv8.5-a+crypto+sve2+lse+crc >> >> Including extensions in march helps compiler generate better code. >> Example adding '+lse' tells the compiler to inline C11 atomics rather >than >> having a run time jump >> >> https://urldefense.proofpoint.com/v2/url?u=3Dhttps- >3A__gcc.godbolt.org_z_8hPv87dbr&d=3DDwIFAg&c=3DnKjWec2b6R0mOyPa >z7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPIDsIJzo6FN6Z0&m=3DUs6Ig >UW0QYnSuSc8dYw0yLXgzYvGHoBD8AKNLX0bzhw&s=3Dmk9V9_YgFBdO23 >6JpZBIN_yhCkYAXGcE_1X315c7jGk&e=3D >Can you compile the code with armv8.5-a instead of armv8-a? I see that >LSE instructions are used. Is LSE extension made mandatory from v8.1? I couldn't find a relevant documentation on ARM website. I have seen some compilers not in lining unless 'lse' is mentioned in march= . The patch still holds true for CRC though as it is listed separately below https://developer.arm.com/architectures/cpu-architecture/a-profile/explorat= ion-tools/feature-names-for-a-profile Also, looks like sve2 support in n2 core might be optional as per above doc= ? >https://urldefense.proofpoint.com/v2/url?u=3Dhttps- >3A__gcc.godbolt.org_z_18MYhY7xv&d=3DDwIFAg&c=3DnKjWec2b6R0mOyP >az7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPIDsIJzo6FN6Z0&m=3DUs6I >gUW0QYnSuSc8dYw0yLXgzYvGHoBD8AKNLX0bzhw&s=3DIpCFzI_hPuBl0P6 >Ylbrfm-1WXvdGg9mwnuzpwC6PrCM&e=3D > >> >> I don't think this is limited to OCTEON 10 other SoC should also add >their >> extensions to march. >> >> > >> >> --- >> >> >> >> More details about ARM extensions >> >> https://urldefense.proofpoint.com/v2/url?u=3Dhttps- >> >>3A__developer.arm.com_documentation_102378_0200&d=3DDwICAg& >c >> >>=3DnKjWec2b6R0mOyPaz7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPID >s >> >>IJzo6FN6Z0&m=3DyCt4te5_7VJvaJT5OXrOpFXH3UBOUqRDlHZuSVEUZH >M >> >&s=3DDquFBMwxMpjxWcM2Qw1c2t_ak-j6DN4rz8ce_I43RJk&e=3D >> >> >> >> config/arm/meson.build | 8 ++++++++ >> >> 1 file changed, 8 insertions(+) >> >> >> >> diff --git a/config/arm/meson.build b/config/arm/meson.build >index >> >> 22cd81319..8aa961e5b 100644 >> >> --- a/config/arm/meson.build >> >> +++ b/config/arm/meson.build >> >> @@ -230,6 +230,7 @@ soc_cn10k =3D { >> >> ['RTE_MAX_LCORE', 24], >> >> ['RTE_MAX_NUMA_NODES', 1] >> >> ], >> >> + 'extensions' : ['lse', 'crc'], >> >> 'part_number': '0xd49', >> >> 'numa': false >> >> } >> >> @@ -387,6 +388,7 @@ else >> >> endif >> >> >> >> soc_flags =3D [] >> >> + soc_extensions =3D [] >> >> if soc_config.has_key('not_supported') >> >> error('SoC @0@ not supported.'.format(soc)) >> >> elif soc_config !=3D {} >> >> @@ -394,6 +396,7 @@ else >> >> implementer_config =3D implementers[implementer_id] >> >> part_number =3D soc_config['part_number'] >> >> soc_flags =3D soc_config.get('flags', []) >> >> + soc_extensions =3D soc_config.get('extensions', []) >> >> if not soc_config.get('numa', true) >> >> has_libnuma =3D 0 >> >> endif >> >> @@ -431,6 +434,11 @@ else >> >> # apply supported machine args >> >> machine_args =3D [] # Clear previous machine args >> >> foreach flag: part_number_config['machine_args'] >> >> + if flag.startswith('-march') and soc_extensions.length() != =3D >> >> + 0 >> > >> >Why condition on start with -march? >> >> There are some implementer flags which don't have -march to add >extensions >> to. >> >> > >> >> + foreach ex: soc_extensions >> >> + flag +=3D '+' + ex >> >> + endforeach >> >> + endif >> > >> >