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Mon, 17 Oct 2022 12:06:54 +0000 From: Shijith Thotton To: Pavan Nikhilesh Bhagavatula , Jerin Jacob Kollanukkaran CC: "dev@dpdk.org" , Pavan Nikhilesh Bhagavatula Subject: RE: [EXT] [PATCH v5 4/5] examples/l3fwd: fix event vector processing in fib Thread-Topic: [EXT] [PATCH v5 4/5] examples/l3fwd: fix event vector processing in fib Thread-Index: AQHY3Vn0qmA09Vt1AUeGM5ZtwM9ilK4Shx5A Date: Mon, 17 Oct 2022 12:06:53 +0000 Message-ID: References: <20221011090805.3602-1-pbhagavatula@marvell.com> <20221011101207.4489-1-pbhagavatula@marvell.com> <20221011101207.4489-4-pbhagavatula@marvell.com> In-Reply-To: <20221011101207.4489-4-pbhagavatula@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR18MB4425:EE_|SJ0PR18MB4946:EE_ x-ms-office365-filtering-correlation-id: 718af3b9-d009-4cd5-263f-08dab03814d5 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: marvell.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR18MB4425.namprd18.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 718af3b9-d009-4cd5-263f-08dab03814d5 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2022 12:06:53.9892 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5wH4ssF1uxnZX4R0DsxiMizkxk9FwkwxOHnKrtUnDxuL2JLFMROlbjWEo7eFt6kG2gbDVY8B6X0y9XCYtibWUQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR18MB4946 X-Proofpoint-ORIG-GUID: _F9nXsINDPBnbkt0_F_BMCFZ6WuMDjOe X-Proofpoint-GUID: _F9nXsINDPBnbkt0_F_BMCFZ6WuMDjOe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-17_09,2022-10-17_02,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > >Fix stack overflow when event vector size is greater than >MAX_BURST_SIZE. >Add missing mac swap and rfc1812 stage. > >Fixes: e8adca1951d4 ("examples/l3fwd: support event vector") > >Signed-off-by: Pavan Nikhilesh Acked-by: Shijith Thotton >--- > examples/l3fwd/l3fwd_fib.c | 130 ++++++++++++++++++++++++++----------- > 1 file changed, 91 insertions(+), 39 deletions(-) > >diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c >index b82e0c0354..edc0dd69b9 100644 >--- a/examples/l3fwd/l3fwd_fib.c >+++ b/examples/l3fwd/l3fwd_fib.c >@@ -77,27 +77,37 @@ fib_parse_packet(struct rte_mbuf *mbuf, > */ > #if !defined FIB_SEND_MULTI > static inline void >-fib_send_single(int nb_tx, struct lcore_conf *qconf, >- struct rte_mbuf **pkts_burst, uint16_t hops[nb_tx]) >+process_packet(struct rte_mbuf *pkt, uint16_t *hop) > { >- int32_t j; > struct rte_ether_hdr *eth_hdr; > >- for (j =3D 0; j < nb_tx; j++) { >- /* Run rfc1812 if packet is ipv4 and checks enabled. */ >+ /* Run rfc1812 if packet is ipv4 and checks enabled. */ > #if defined DO_RFC_1812_CHECKS >- rfc1812_process((struct rte_ipv4_hdr *)(rte_pktmbuf_mtod( >- pkts_burst[j], struct rte_ether_hdr *) + 1), >- &hops[j], pkts_burst[j]->packet_type); >+ rfc1812_process( >+ (struct rte_ipv4_hdr *)(rte_pktmbuf_mtod( >+ pkt, struct rte_ether_hdr *) + >+ 1), >+ hop, pkt->packet_type); > #endif > >- /* Set MAC addresses. */ >- eth_hdr =3D rte_pktmbuf_mtod(pkts_burst[j], >- struct rte_ether_hdr *); >- *(uint64_t *)ð_hdr->dst_addr =3D dest_eth_addr[hops[j]]; >- rte_ether_addr_copy(&ports_eth_addr[hops[j]], >- ð_hdr->src_addr); >+ /* Set MAC addresses. */ >+ eth_hdr =3D rte_pktmbuf_mtod(pkt, struct rte_ether_hdr *); >+ *(uint64_t *)ð_hdr->dst_addr =3D dest_eth_addr[*hop]; >+ rte_ether_addr_copy(&ports_eth_addr[*hop], ð_hdr->src_addr); >+} > >+static inline void >+fib_send_single(int nb_tx, struct lcore_conf *qconf, >+ struct rte_mbuf **pkts_burst, uint16_t hops[nb_tx]) >+{ >+ int32_t j; >+ >+ for (j =3D 0; j < nb_tx; j++) { >+ process_packet(pkts_burst[j], &hops[j]); >+ if (hops[j] =3D=3D BAD_PORT) { >+ rte_pktmbuf_free(pkts_burst[j]); >+ continue; >+ } > /* Send single packet. */ > send_single_packet(qconf, pkts_burst[j], hops[j]); > } >@@ -261,7 +271,7 @@ fib_event_loop(struct l3fwd_event_resources *evt_rsrc, > uint32_t ipv4_arr[MAX_PKT_BURST]; > uint8_t ipv6_arr[MAX_PKT_BURST][RTE_FIB6_IPV6_ADDR_SIZE]; > uint64_t hopsv4[MAX_PKT_BURST], hopsv6[MAX_PKT_BURST]; >- uint16_t nh; >+ uint16_t nh, hops[MAX_PKT_BURST]; > uint8_t type_arr[MAX_PKT_BURST]; > uint32_t ipv4_cnt, ipv6_cnt; > uint32_t ipv4_arr_assem, ipv6_arr_assem; >@@ -350,7 +360,13 @@ fib_event_loop(struct l3fwd_event_resources *evt_rsrc= , > else > nh =3D (uint16_t)hopsv6[ipv6_arr_assem++]; > if (nh !=3D FIB_DEFAULT_HOP) >- events[i].mbuf->port =3D nh; >+ hops[i] =3D nh !=3D FIB_DEFAULT_HOP ? >+ nh : >+ events[i].mbuf->port; >+ process_packet(events[i].mbuf, &hops[i]); >+ events[i].mbuf->port =3D hops[i] !=3D BAD_PORT ? >+ hops[i] : >+ events[i].mbuf->port; > } > > if (flags & L3FWD_EVENT_TX_ENQ) { >@@ -418,14 +434,12 @@ fib_event_main_loop_tx_q_burst(__rte_unused void >*dummy) > } > > static __rte_always_inline void >-fib_process_event_vector(struct rte_event_vector *vec) >+fib_process_event_vector(struct rte_event_vector *vec, uint8_t *type_arr, >+ uint8_t **ipv6_arr, uint64_t *hopsv4, uint64_t *hopsv6, >+ uint32_t *ipv4_arr, uint16_t *hops) > { >- uint8_t ipv6_arr[MAX_PKT_BURST][RTE_FIB6_IPV6_ADDR_SIZE]; >- uint64_t hopsv4[MAX_PKT_BURST], hopsv6[MAX_PKT_BURST]; > uint32_t ipv4_arr_assem, ipv6_arr_assem; > struct rte_mbuf **mbufs =3D vec->mbufs; >- uint32_t ipv4_arr[MAX_PKT_BURST]; >- uint8_t type_arr[MAX_PKT_BURST]; > uint32_t ipv4_cnt, ipv6_cnt; > struct lcore_conf *lconf; > uint16_t nh; >@@ -463,16 +477,10 @@ fib_process_event_vector(struct rte_event_vector >*vec) > > /* Lookup IPv6 hops if IPv6 packets are present. */ > if (ipv6_cnt > 0) >- rte_fib6_lookup_bulk(lconf->ipv6_lookup_struct, ipv6_arr, >- hopsv6, ipv6_cnt); >- >- if (vec->attr_valid) { >- nh =3D type_arr[0] ? (uint16_t)hopsv4[0] : (uint16_t)hopsv6[0]; >- if (nh !=3D FIB_DEFAULT_HOP) >- vec->port =3D nh; >- else >- vec->attr_valid =3D 0; >- } >+ rte_fib6_lookup_bulk( >+ lconf->ipv6_lookup_struct, >+ (uint8_t(*)[RTE_FIB6_IPV6_ADDR_SIZE])ipv6_arr, hopsv6, >+ ipv6_cnt); > > /* Assign ports looked up in fib depending on IPv4 or IPv6 */ > for (i =3D 0; i < vec->nb_elem; i++) { >@@ -481,9 +489,26 @@ fib_process_event_vector(struct rte_event_vector *vec= ) > else > nh =3D (uint16_t)hopsv6[ipv6_arr_assem++]; > if (nh !=3D FIB_DEFAULT_HOP) >- mbufs[i]->port =3D nh; >- event_vector_attr_validate(vec, mbufs[i]); >+ hops[i] =3D nh; >+ else >+ hops[i] =3D vec->attr_valid ? vec->port : >+ vec->mbufs[i]->port; > } >+ >+#if defined FIB_SEND_MULTI >+ uint16_t k; >+ k =3D RTE_ALIGN_FLOOR(vec->nb_elem, FWDSTEP); >+ >+ for (i =3D 0; i !=3D k; i +=3D FWDSTEP) >+ processx4_step3(&vec->mbufs[i], &hops[i]); >+ for (; i < vec->nb_elem; i++) >+ process_packet(vec->mbufs[i], &hops[i]); >+#else >+ for (i =3D 0; i < vec->nb_elem; i++) >+ process_packet(vec->mbufs[i], &hops[i]); >+#endif >+ >+ process_event_vector(vec, hops); > } > > static __rte_always_inline void >@@ -496,10 +521,37 @@ fib_event_loop_vector(struct l3fwd_event_resources >*evt_rsrc, > const uint8_t event_d_id =3D evt_rsrc->event_d_id; > const uint16_t deq_len =3D evt_rsrc->deq_depth; > struct rte_event events[MAX_PKT_BURST]; >+ uint8_t *type_arr, **ipv6_arr, *ptr; > int nb_enq =3D 0, nb_deq =3D 0, i; >- >- if (event_p_id < 0) >+ uint64_t *hopsv4, *hopsv6; >+ uint32_t *ipv4_arr; >+ uint16_t *hops; >+ uintptr_t mem; >+ >+ mem =3D (uintptr_t)rte_zmalloc( >+ "vector_fib", >+ (sizeof(uint32_t) + sizeof(uint8_t) + sizeof(uint64_t) + >+ sizeof(uint64_t) + sizeof(uint16_t) + sizeof(uint8_t *) + >+ (sizeof(uint8_t) * RTE_FIB6_IPV6_ADDR_SIZE)) * >+ evt_rsrc->vector_size, >+ RTE_CACHE_LINE_SIZE); >+ if (mem =3D=3D 0) > return; >+ ipv4_arr =3D (uint32_t *)mem; >+ type_arr =3D (uint8_t *)&ipv4_arr[evt_rsrc->vector_size]; >+ hopsv4 =3D (uint64_t *)&type_arr[evt_rsrc->vector_size]; >+ hopsv6 =3D (uint64_t *)&hopsv4[evt_rsrc->vector_size]; >+ hops =3D (uint16_t *)&hopsv6[evt_rsrc->vector_size]; >+ ipv6_arr =3D (uint8_t **)&hops[evt_rsrc->vector_size]; >+ >+ ptr =3D (uint8_t *)&ipv6_arr[evt_rsrc->vector_size]; >+ for (i =3D 0; i < evt_rsrc->vector_size; i++) >+ ipv6_arr[i] =3D &ptr[RTE_FIB6_IPV6_ADDR_SIZE + i]; >+ >+ if (event_p_id < 0) { >+ rte_free((void *)mem); >+ return; >+ } > > RTE_LOG(INFO, L3FWD, "entering %s on lcore %u\n", __func__, > rte_lcore_id()); >@@ -519,10 +571,9 @@ fib_event_loop_vector(struct l3fwd_event_resources >*evt_rsrc, > events[i].op =3D RTE_EVENT_OP_FORWARD; > } > >- fib_process_event_vector(events[i].vec); >- >- if (flags & L3FWD_EVENT_TX_DIRECT) >- event_vector_txq_set(events[i].vec, 0); >+ fib_process_event_vector(events[i].vec, type_arr, >+ ipv6_arr, hopsv4, hopsv6, >+ ipv4_arr, hops); > } > > if (flags & L3FWD_EVENT_TX_ENQ) { >@@ -546,6 +597,7 @@ fib_event_loop_vector(struct l3fwd_event_resources >*evt_rsrc, > > l3fwd_event_worker_cleanup(event_d_id, event_p_id, events, nb_enq, > nb_deq, 1); >+ rte_free((void *)mem); > } > > int __rte_noinline >-- >2.25.1