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From: "Xu, Ke1" <ke1.xu@intel.com>
To: "Ye, MingjinX" <mingjinx.ye@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Yang, Qiming" <qiming.yang@intel.com>,
	"Zhou, YidingX" <yidingx.zhou@intel.com>,
	"Ye, MingjinX" <mingjinx.ye@intel.com>,
	"Zhang, Qi Z" <qi.z.zhang@intel.com>
Subject: RE: [PATCH v2] net/ice: support double vlan
Date: Fri, 26 May 2023 10:16:28 +0000	[thread overview]
Message-ID: <PH7PR11MB6056C83729D8B707B5669451D3479@PH7PR11MB6056.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230506100443.215817-1-mingjinx.ye@intel.com>

> From: Mingjin Ye <mingjinx.ye@intel.com>
> Sent: Saturday, May 6, 2023 6:05 PM
> To: dev@dpdk.org
> Cc: Yang, Qiming <qiming.yang@intel.com>; Zhou, YidingX
> <yidingx.zhou@intel.com>; Ye, MingjinX <mingjinx.ye@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [PATCH v2] net/ice: support double vlan
> 
> Aligned with kernel driver, optimized for inner and outer VLAN handling in DPDK,
> and implemented double vlan insertion and stripping support.
> NIC must work in double vlan mode(DVM), depending on FW/SW.
> 
> 1. Adjust vlan stripping
> The vlan stripping enable/disable is applied to the inner vlan.
> 
> 2. Support QinQ stripping
> The ice outer vlan strip is enabled/disabled by the mask bit of
> `RTE_ETH_RX_OFFLOAD_QINQ_STRIP`, and the user can use "vlan set qinq_strip
> on 0" to enable or "vlan setqinq_strip off 0" to disable the ice outer vlan strip in
> testpmd.
> 
> 3. Support outer tag type switching
> Implement the ethdev `vlan_tpid_set` api to enable outer tag support to handle
> `RTE_ETHER_TYPE_VLAN`` RTE_ETHER_TYPE_QINQ`` RTE_ETHER_TYPE_QINQ1`
> outer tag types.
> 
> 4. Support outer port-based vlan insertion Implement port-based outer vlan
> insertion. User can use "tx_vlan set pvid 0 45 on" to enable or "tx_vlan set pvid 0
> 45 off" to disable the outer vlan insertion in testpmd.
> 
> Signed-off-by: Mingjin Ye <mingjinx.ye@intel.com>

Tested and passed.

There are several points need to be mentioned.
1. Only Scalar path is implemented, needs force-max-simd-bitwidth.
2. Not supported: StripQ.
3. Hardware limitation: Requires different outer and inner VLAN type. It means
  setting outer TPID to 0x88a8 before double VLAN insert.
4. Undefined behaviour: VLAN insert and TPID configured together is not defined
  in this new feature. TPID is designed to work with PVID now. Under this implementation
  changing TPID would not change the TX outer VLAN type of double VLAN insert.

Tested-by: Ke Xu <ke1.xu@intel.com>

> ---
> v2: Apply QinQ when initializing vlan offload.
> ---
>  drivers/net/ice/ice_ethdev.c | 422 +++++++++++++++++++++++++++++++++--
>  drivers/net/ice/ice_ethdev.h |   1 +
>  2 files changed, 408 insertions(+), 15 deletions(-)
> 


  reply	other threads:[~2023-05-26 10:16 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-20  6:16 [PATCH] net/ice: CVL " Mingjin Ye
2023-05-06 10:04 ` [PATCH v2] net/ice: " Mingjin Ye
2023-05-26 10:16   ` Xu, Ke1 [this message]
2023-05-26 11:10     ` Zhang, Qi Z
2023-07-17  9:36 ` [POC] net/iavf: support no data path polling mode Mingjin Ye
2023-07-20 10:08   ` [POC v2] " Mingjin Ye
2023-07-20 15:45     ` Stephen Hemminger
2023-07-21  9:57     ` [POC v3] " Mingjin Ye
2023-08-11  6:27       ` [PATCH] " Mingjin Ye
2023-09-26  7:56         ` [PATCH v2] " Mingjin Ye
2023-10-13  1:27           ` [PATCH v3] " Mingjin Ye
2023-10-17  1:44             ` [PATCH v4] " Mingjin Ye
2023-10-17  2:19             ` Mingjin Ye
2023-10-19  9:04               ` [PATCH v5] net/iavf: data paths support no-polling mode Mingjin Ye
2023-10-20  0:39                 ` Zhang, Qi Z

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