From: "Varghese, Vipin" <Vipin.Varghese@amd.com>
To: "Honnappa Nagarahalli" <Honnappa.Nagarahalli@arm.com>,
"Mattias Rönnblom" <hofors@lysator.liu.se>
Cc: "Yigit, Ferruh" <Ferruh.Yigit@amd.com>,
"dev@dpdk.org" <dev@dpdk.org>, nd <nd@arm.com>
Subject: RE: [RFC 0/2] introduce LLC aware functions
Date: Thu, 12 Sep 2024 02:28:53 +0000 [thread overview]
Message-ID: <PH7PR12MB85963470504E17D2D3365A1282642@PH7PR12MB8596.namprd12.prod.outlook.com> (raw)
In-Reply-To: <716375DE-0C2F-4983-934A-144D7DE342C6@arm.com>
[Public]
<snipped>
> > What use case do you have in mind? What's on top of my list is a scenario
> where a DPDK app gets a bunch of cores (e.g., -l <cores>) and tries to figure
> out how best make use of them. It's not going to "skip" (ignore, leave unused)
> SMT siblings, or skip non-boosted cores, it would just try to be clever in
> regards to which cores to use for what purpose.
> >
> >> This is AMD EPYC SoC agnostic and trying to address for all generic cases.
> >> Please do let us know if we (Ferruh & myself) can sync up via call?
> >
> > Sure, I can do that.
> >
> Can this be opened to the rest of the community? This is a common problem
> that needs to be solved for multiple architectures. I would be interested in
> attending.
Hi Honappa, we can accommodate the same. Let me work with Ferruh how to get it as tech discussion.
<snipped>
next prev parent reply other threads:[~2024-09-12 2:28 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-27 15:10 Vipin Varghese
2024-08-27 15:10 ` [RFC 1/2] eal: add llc " Vipin Varghese
2024-08-27 17:36 ` Stephen Hemminger
2024-09-02 0:27 ` Varghese, Vipin
2024-08-27 20:56 ` Wathsala Wathawana Vithanage
2024-08-29 3:21 ` 答复: " Feifei Wang
2024-09-02 1:20 ` Varghese, Vipin
2024-09-03 17:54 ` Wathsala Wathawana Vithanage
2024-09-04 8:18 ` Bruce Richardson
2024-09-06 11:59 ` Varghese, Vipin
2024-09-12 16:58 ` Wathsala Wathawana Vithanage
2024-08-27 15:10 ` [RFC 2/2] eal/lcore: add llc aware for each macro Vipin Varghese
2024-08-27 21:23 ` [RFC 0/2] introduce LLC aware functions Mattias Rönnblom
2024-09-02 0:39 ` Varghese, Vipin
2024-09-04 9:30 ` Mattias Rönnblom
2024-09-04 14:37 ` Stephen Hemminger
2024-09-11 3:13 ` Varghese, Vipin
2024-09-11 3:53 ` Stephen Hemminger
2024-09-12 1:11 ` Varghese, Vipin
2024-09-09 14:22 ` Varghese, Vipin
2024-09-09 14:52 ` Mattias Rönnblom
2024-09-11 3:26 ` Varghese, Vipin
2024-09-11 15:55 ` Mattias Rönnblom
2024-09-11 17:04 ` Honnappa Nagarahalli
2024-09-12 1:33 ` Varghese, Vipin
2024-09-12 6:38 ` Mattias Rönnblom
2024-09-12 7:02 ` Mattias Rönnblom
2024-09-12 11:23 ` Varghese, Vipin
2024-09-12 12:12 ` Mattias Rönnblom
2024-09-12 15:50 ` Stephen Hemminger
2024-09-12 11:17 ` Varghese, Vipin
2024-09-12 11:59 ` Mattias Rönnblom
2024-09-12 13:30 ` Bruce Richardson
2024-09-12 16:32 ` Mattias Rönnblom
2024-09-12 2:28 ` Varghese, Vipin [this message]
2024-09-11 16:01 ` Bruce Richardson
2024-09-11 22:25 ` Konstantin Ananyev
2024-09-12 2:38 ` Varghese, Vipin
2024-09-12 2:19 ` Varghese, Vipin
2024-09-12 9:17 ` Bruce Richardson
2024-09-12 11:50 ` Varghese, Vipin
2024-09-13 14:15 ` Burakov, Anatoly
2024-09-12 13:18 ` Mattias Rönnblom
2024-08-28 8:38 ` Burakov, Anatoly
2024-09-02 1:08 ` Varghese, Vipin
2024-09-02 14:17 ` Burakov, Anatoly
2024-09-02 15:33 ` Varghese, Vipin
2024-09-03 8:50 ` Burakov, Anatoly
2024-09-05 13:05 ` Ferruh Yigit
2024-09-05 14:45 ` Burakov, Anatoly
2024-09-05 15:34 ` Ferruh Yigit
2024-09-06 8:44 ` Burakov, Anatoly
2024-09-09 14:14 ` Varghese, Vipin
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