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boundary="_000_PH7PR12MB8596676D8F96D7F8E13D15E682642PH7PR12MB8596namp_" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR12MB8596.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e039bc6-5a0a-4675-68df-08dcd2d3efb7 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2024 02:38:08.1285 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GHcCAy6uUGJvX8IqpVGrz20g6QzMOVEe7EPt80QGkmWikDt0CIAJXQiwfPBcLsnYBLtMvCpnMNEAxixVOeZp4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6754 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --_000_PH7PR12MB8596676D8F96D7F8E13D15E682642PH7PR12MB8596namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - AMD Internal Distribution Only] > > > > For the naming, would "rte_get_next_sibling_core" (or lcore if you > > prefer) be a clearer name than just adding "ex" on to the end of the > > existing function? > > > > Looking logically, I'm not sure about the BOOST_ENABLED and > > BOOST_DISABLED flags you propose - in a system with multiple possible > > standard and boost frequencies what would those correspond to? What's > > also missing is a define for getting actual NUMA siblings i.e. those > > sharing common memory but not an L3 or anything else. > > > > My suggestion would be to have the function take just an integer-type e= .g. > > uint16_t parameter which defines the memory/cache hierarchy level to > > use, 0 being lowest, 1 next, and so on. Different systems may have > > different numbers of cache levels so lets just make it a zero-based > > index of levels, rather than giving explicit defines (except for > > memory which should probably always be last). The zero-level will be fo= r > "closest neighbour" > > whatever that happens to be, with as many levels as is necessary to > > express the topology, e.g. without SMT, but with 3 cache levels, level > > 0 would be an L2 neighbour, level 1 an L3 neighbour. If the L3 was > > split within a memory NUMA node, then level 2 would give the NUMA > > siblings. We'd just need an API to return the max number of levels alon= g with > the iterator. > > Sounds like a neat idea to me. Hi Konstantin, I have tried my best to address to Bruce comment. Let me try= to recap 1. we want vendor agnostic API which allows end users to get list of l= cores 2. this can be based on L1(SMT), L2, L3, NUMA, TURBO (as of now) 3. instead of creating multiple different API, we would like to add 1 = API `rte_get_next_lcore_extnd` which can be controlled with `flags` 4. flag can be single or combination (like L3|TURBO_ENABLED or NUMA|TU= RBO_ENABLED). 5. As per my current idea, we can expand ease of use via MACRO and not= API. I hope this justifies why we should have 1 exntended API and wrap things wi= th Macro? May I setup or add to tech discussion call with Mattias and Honappa too? --_000_PH7PR12MB8596676D8F96D7F8E13D15E682642PH7PR12MB8596namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
[AM= D Official Use Only - AMD Internal Distribution Only]

<= snipped>
>= >
>= > For the naming, would "rte_get_next_sibling_core" (or lcore= if you
>= > prefer) be a clearer name than just adding "ex" on to the e= nd of the
>= > existing function?
>= >
>= > Looking logically, I'm not sure about the BOOST_ENABLED and
>= > BOOST_DISABLED flags you propose - in a system with multiple possible=
>= > standard and boost frequencies what would those correspond to? What's=
>= > also missing is a define for getting actual NUMA siblings i.e. those<= /span>
>= > sharing common memory but not an L3 or anything else.
>= >
>= > My suggestion would be to have the function take just an integer-type= e.g.
>= > uint16_t parameter which defines the memory/cache hierarchy level to<= /span>
>= > use, 0 being lowest, 1 next, and so on. Different systems may have
>= > different numbers of cache levels so lets just make it a zero-based
>= > index of levels, rather than giving explicit defines (except for
>= > memory which should probably always be last). The zero-level will be = for
>= "closest neighbour"
>= > whatever that happens to be, with as many levels as is necessary to
>= > express the topology, e.g. without SMT, but with 3 cache levels, leve= l
>= > 0 would be an L2 neighbour, level 1 an L3 neighbour. If the L3 was
>= > split within a memory NUMA node, then level 2 would give the NUMA
>= > siblings. We'd just need an API to return the max number of levels al= ong with
>= the iterator.
>=
>= Sounds like a neat idea to me.
&nbs= p;
Hi K= onstantin, I have tried my best to address to Bruce comment. Let me try to = recap
  1. we want vendor agnostic API which allows end users to get list of lcore= s
  2. this can be based on L1(SMT), L2, L3, NUMA, TURBO (as of now)
  3. instead of creating multiple different API, we would like to add 1 API= `rte_get_next_lcore_extnd` which can be controlled with `flags`
  4. fl= ag can be single or combination (like L3|TURBO_ENABLED or NUMA|TURBO_ENABLE= D).
  5. As per my current idea, we can expand ease of use via MACRO and= not API.
    6.
&nbs= p;
I ho= pe this justifies why we should have 1 exntended API and wrap things with M= acro?
May = I setup or add to tech discussion call with Mattias and Honappa too?=
--_000_PH7PR12MB8596676D8F96D7F8E13D15E682642PH7PR12MB8596namp_--