[AMD Official Use Only - AMD Internal Distribution Only]
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> > >
> > > Thank you Mattias for the comments and question, please let me try
> > > to explain the same below
> > >
> > >> We shouldn't have a separate CPU/cache hierarchy API instead?
> > >
> > > Based on the intention to bring in CPU lcores which share same L3
> > > (for better cache hits and less noisy neighbor) current API focuses
> > > on using
> > >
> > > Last Level Cache. But if the suggestion is `there are SoC where L2
> > > cache are also shared, and the new API should be provisioned`, I am
> > > also
> > >
> > > comfortable with the thought.
> > >
> >
> > Rather than some AMD special case API hacked into <rte_lcore.h>, I
> > think we are better off with no DPDK API at all for this kind of functionality.
> >
> > A DPDK CPU/memory hierarchy topology API very much makes sense, but it
> > should be reasonably generic and complete from the start.
>
> Agreed. This one of those cases where the existing project hwloc which is part
> of open-mpi is more complete and well supported. It supports multiple OS's
> and can deal with more quirks.
Thank you Stephen for the inputs, last year when checked hwloc for distros there were anomalies for NUMA and Physical socket Identification on AMD EPYC Soc.
I will recheck the distros version of hwloc, if these work out fine I will re-work with hwloc libraries making it OS independent too.
>