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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR12MB8596.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f60bdfd4-9756-4218-2c8c-08dda74d0e68 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jun 2025 11:59:15.2202 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: u8GOtSZ5QnijXaVFf3w+0zwZJQTWWw65FcFi5uJ0h//0wPCkl2cqtfE66EbU4OeXF/JjdC/2YVe/YE7dZ4EUWg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6528 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org [AMD Official Use Only - AMD Internal Distribution Only] > -----Original Message----- > From: Bruce Richardson > Sent: Monday, June 9, 2025 1:28 PM > To: Varghese, Vipin > Cc: dev@dpdk.org; Song, Keesang > Subject: Re: [PATCH v4] build: reduce use of AVX compiler flags > > Caution: This message originated from an External Source. Use proper caut= ion > when opening attachments, clicking links, or responding. > > > On Mon, Jun 09, 2025 at 06:02:02AM +0000, Varghese, Vipin wrote: > > [Public] > > > > Snipped > > > > > > > > > > > When doing a build for a target that already has the instruction > > > sets for > > > AVX2/AVX512 enabled, skip emitting the AVX compiler flags, or the > > > skylake-avx512 '-march' flags, as they are unnecessary. Instead, > > > when the default flags produce the desired output, just use them > > > unmodified, and don't bother adding in extra enabling flags for AVX2 = or AVX-512. > > > > > > Depends-on: series-35006 ("doc/linux_gsg: update recommended > > > compiler > > > versions") > > > > > > Signed-off-by: Bruce Richardson > > > --- > > > > > > V4: Fix error flagged by CI with clang builds without AVX512 - change > > > "cc_avx512_args" to correct "cc_avx512_flags" > > > > > > V3: put in version check to work around an issues with some meson > > > versions, (hopefully) allowing builds to pass in all CIs. The > > > printout of the extra flags now only happens with meson >=3D > > > 0.60.2 > > > > > > V2: dropped the doc update for the minimum compiler version. Based o= n > > > discussion, that version bump is larger than proposed in RFC and = is > > > now a separate patch/series [series 35006 referenced above] > > > > > > --- > > > config/x86/meson.build | 31 ++++++++++++++++++++----------- > > > drivers/meson.build | 9 +-------- > > > lib/meson.build | 9 +-------- > > > 3 files changed, 22 insertions(+), 27 deletions(-) > > > > > > diff --git a/config/x86/meson.build b/config/x86/meson.build index > > > c3564b0011..e6612dbd80 100644 > > > --- a/config/x86/meson.build > > > +++ b/config/x86/meson.build > > > @@ -4,11 +4,13 @@ > > > if is_ms_compiler > > > cc_avx2_flags =3D ['/arch:AVX2'] > > > else > > > - cc_avx2_flags =3D ['-mavx2'] > > > + cc_avx2_flags =3D [] > > > + if cc.get_define('__AVX2__', args: machine_args) =3D=3D '' > > > + cc_avx2_flags =3D ['-mavx2'] > > > + endif > > > endif > > > > > > cc_has_avx512 =3D false > > > -target_has_avx512 =3D false > > > > > > dpdk_conf.set('RTE_ARCH_X86', 1) > > > if dpdk_conf.get('RTE_ARCH_64') > > > @@ -65,26 +67,33 @@ if is_linux or cc.get_id() =3D=3D 'gcc' > > > endif > > > endif > > > > > > -cc_avx512_flags =3D ['-mavx512f', '-mavx512vl', '-mavx512dq', > > > '-mavx512bw', '- mavx512cd'] -if (binutils_ok and > > > cc.has_multi_arguments(cc_avx512_flags) > > > +avx512_march_flag =3D '-march=3Dskylake-avx512' > > > +cc_avx512_flags =3D [] > > > +if (binutils_ok and cc.has_argument(avx512_march_flag) > > > and '-mno-avx512f' not in get_option('c_args')) > > > # check if compiler is working with _mm512_extracti64x4_epi64 > > > # Ref: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D82887 > > > code =3D '''#include > > > void test(__m512i zmm){ > > > __m256i ymm =3D _mm512_extracti64x4_epi64(zmm, 0);}''' > > > - result =3D cc.compiles(code, args : cc_avx512_flags, name : 'AVX= 512 > checking') > > > + result =3D cc.compiles(code, args : [avx512_march_flag], name : > > > + 'AVX512 checking') > > > if result =3D=3D false > > > machine_args +=3D '-mno-avx512f' > > > warning('Broken _mm512_extracti64x4_epi64, disabling AVX512 = support') > > > else > > > cc_has_avx512 =3D true > > > - target_has_avx512 =3D ( > > > - cc.get_define('__AVX512F__', args: machine_args) != =3D '' and > > > - cc.get_define('__AVX512BW__', args: machine_args) != =3D '' and > > > - cc.get_define('__AVX512DQ__', args: machine_args) != =3D '' and > > > - cc.get_define('__AVX512VL__', args: machine_args) != =3D '' > > > - ) > > > + if cc.get_define('__AVX512F__', args: machine_args) =3D=3D '= ' > > > + cc_avx512_flags =3D [avx512_march_flag] > > > > Hi Bruce, we have reviewed this internally and tested the same. We woul= d like > your thought for the following. > > > > - Before patch: we were directly setting AVX512 falgs for F, BW, DQ, > > VL > > - new patch: we are setting the flags for `skylake-server` as bare mini= mal. > > - AMD supports AVX512 from `znver4 and higher`. > > > > As per GCC `https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html`, the e= xtra ISA > supported between skylake-server (super set) and znver4 and znver5 are `S= AHF, > FXSR, XSAVE, RDRND, LZCNT, HLE, PREFETCHW, SGX`. > > Currently for DPDK microbenchmarks and examples runs safe as it is not = using > the `SAHF, FXSR, XSAVE, RDRND, LZCNT, HLE, PREFETCHW, SGX` > instructions. > > > > Question: should we check if target is `AMD EPYC` then apply bare minim= um as > `-march=3Dznver4`, thus avoid possible unsupported instruction generation= when non > `c_args for march` is passed? > > > > Can you clarify why you mean by the "target" here? Is there a specific va= lue you > are thinking of for the "cpu_instruction_set" option? `Target` is target CPU, when generated without any arguments we get code fo= r `native build`. On AMD target cpu zen4 or zen5; Before patch as per the code ` AVX512 flags= for F, BW, DQ` are used in ` cc_avx512_flags`. With the patch, the cc_avx512_flags is set to `-march=3Dskylake-avx512` (wh= ere compiler optimizations `can add HLE, PREFETCHW, SGX`). Note: in our current testing for dpdk app and a few examples, we have not e= ncountered the same yet. But there might be projects where compiler may add= those instructions which are unsupported in `AMD EPYC`. Hence the question we are asking is, `should we check if target is AMD-EPYC= , if yes use -march=3Dznver4 instead of -march=3Dskylake-server`? > > /Bruce