From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from dpdk.org (dpdk.org [92.243.14.124])
by inbox.dpdk.org (Postfix) with ESMTP id 4FE26A0597;
Wed, 8 Apr 2020 23:26:16 +0200 (CEST)
Received: from [92.243.14.124] (localhost [127.0.0.1])
by dpdk.org (Postfix) with ESMTP id 45B9E1C1F0;
Wed, 8 Apr 2020 23:26:15 +0200 (CEST)
Received: from mga18.intel.com (mga18.intel.com [134.134.136.126])
by dpdk.org (Postfix) with ESMTP id 68B0D1C1EF
for <dev@dpdk.org>; Wed, 8 Apr 2020 23:26:12 +0200 (CEST)
IronPort-SDR: PdmVXIzJoMGEm/PDlTf69jqt6MwOEHGwKM97Wtk6PISpl60cPNnM5oGdTuO7E+JIMKAdAyk8wP
Ltw146svhhfg==
X-Amp-Result: SKIPPED(no attachment in message)
X-Amp-File-Uploaded: False
Received: from fmsmga004.fm.intel.com ([10.253.24.48])
by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
08 Apr 2020 14:26:10 -0700
IronPort-SDR: oAOgV6thA+Y5TGfCllQ+DK0vRoHwF6pSAuegqjvzJK2CTkDtGy4EmfxBTL8uxzlerPVVGDXmOc
X/oA9FYiBxsg==
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.72,359,1580803200"; d="scan'208";a="275580379"
Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204])
by fmsmga004.fm.intel.com with ESMTP; 08 Apr 2020 14:26:09 -0700
Received: from fmsmsx603.amr.corp.intel.com (10.18.126.83) by
FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS)
id 14.3.439.0; Wed, 8 Apr 2020 14:26:09 -0700
Received: from fmsmsx608.amr.corp.intel.com (10.18.126.88) by
fmsmsx603.amr.corp.intel.com (10.18.126.83) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id
15.1.1713.5; Wed, 8 Apr 2020 14:26:08 -0700
Received: from FMSEDG001.ED.cps.intel.com (10.1.192.133) by
fmsmsx608.amr.corp.intel.com (10.18.126.88) with Microsoft SMTP Server
(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5
via Frontend Transport; Wed, 8 Apr 2020 14:26:08 -0700
Received: from NAM04-SN1-obe.outbound.protection.outlook.com (104.47.44.59) by
edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server
(TLS) id 14.3.439.0; Wed, 8 Apr 2020 14:26:08 -0700
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
b=Cr5pU/sfHOLtTb2w2eTup+blP3g3i0J+twQvb0T4D/h5G9CBlwWH9YAYnv0uj/Vg64bHU3pe+SZ8osfnTdrNZhhVDXKScmYUs547kQFHVeAQ+oYbrUqi53sy2r0fz93kNhzmC7iN5araNv2CpVBQ3fQUh+A9JmKLsXDO8pBx51cnkBcFktSMW6ozQDC0+yvFIS6Wu9Sk23enszYe0LUmyosV7po9a/U4SwdvhyDz7S/9MSEn7V9J7kXXsZ1gwwnjkKWbS/9418tqscMuY3cwML8iJUi2V8pQUTDElVq0CSvea+/7OU7g9p8G6U0I281UJmP3/lQRsHdjrmvU/UsuOw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector9901;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=7JbvcvImbjpEMb6uBoUCGlb+80MQAfx7KmJIvC8gKNc=;
b=AbZh9/136o+vzAXXYrTofpEK0qJTYPDt5N7lDO/LZ8rWzrYpTPWp63fxw6qzOTEGV+qzwbgCQhyDXRV+rfAQEamiPP8a/5ZbrjviZh917lrfZNCwljBA+t0H0EhGk8vLY3vY/Wby5xcZ598PlpcwnjRpOqYX+i0uBJ3TV9CWnthghzRwesbBR/Uz/6g2DlcEpp2ojBehdlyWwrAbOQh/Nhr8dyxQFFbq5pQ9juBj+k8jBTz2V9o5hrOako8vXPinSBUI0nrlgk4aOKQ18picqgogLmlOHv0mOyV2MSOTWe1SgWriLx6EHe+rpp8T2uGv6JGN9I6gVFekimqwD4eXew==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass
smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com;
dkim=pass header.d=intel.com; arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com;
s=selector2-intel-onmicrosoft-com;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=7JbvcvImbjpEMb6uBoUCGlb+80MQAfx7KmJIvC8gKNc=;
b=j0ggBZa1yrJ6/2Q8QsGuPIPONPQM3sgSigJE9FiUn/QS21fEULyR9EL4tdja7q2MJL66iWLK9QGkH+thmWGNmIrxDrLnl9z5UQFY4oBSTKCp2JLjsLwjASsAwUamnVkwZXAPcKTikxXXHi/7lXWSD+oJq9WlZ65Sv+xsAmIJ3oI=
Received: from SA0PR11MB4656.namprd11.prod.outlook.com (2603:10b6:806:96::23)
by SA0PR11MB4736.namprd11.prod.outlook.com (2603:10b6:806:9f::14)
with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2878.20; Wed, 8 Apr
2020 21:26:04 +0000
Received: from SA0PR11MB4656.namprd11.prod.outlook.com
([fe80::6400:b873:7752:50b4]) by SA0PR11MB4656.namprd11.prod.outlook.com
([fe80::6400:b873:7752:50b4%4]) with mapi id 15.20.2878.018; Wed, 8 Apr 2020
21:26:04 +0000
From: "Carrillo, Erik G" <erik.g.carrillo@intel.com>
To: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, Phil Yang
<Phil.Yang@arm.com>, "rsanford@akamai.com" <rsanford@akamai.com>,
"dev@dpdk.org" <dev@dpdk.org>
CC: "david.marchand@redhat.com" <david.marchand@redhat.com>, "Burakov,
Anatoly" <anatoly.burakov@intel.com>, "thomas@monjalon.net"
<thomas@monjalon.net>, "jerinj@marvell.com" <jerinj@marvell.com>,
"hemant.agrawal@nxp.com" <hemant.agrawal@nxp.com>, Gavin Hu
<Gavin.Hu@arm.com>, nd <nd@arm.com>, nd <nd@arm.com>
Thread-Topic: [PATCH 2/2] lib/timer: relax barrier for status update
Thread-Index: AQHV6t2yBm1KhrbDIU2DdShJp9K8ZKhv+ljQgAAFyYCAAACa4A==
Date: Wed, 8 Apr 2020 21:26:04 +0000
Message-ID: <SA0PR11MB4656F6FC8DC23AAA4017B4C0B9C00@SA0PR11MB4656.namprd11.prod.outlook.com>
References: <1582526539-14360-1-git-send-email-phil.yang@arm.com>
<1582526539-14360-2-git-send-email-phil.yang@arm.com>
<SA0PR11MB4656BE7ABFD897F7168C5CA3B9C00@SA0PR11MB4656.namprd11.prod.outlook.com>
<DBBPR08MB464664C773AFF2B57C3017A598C00@DBBPR08MB4646.eurprd08.prod.outlook.com>
In-Reply-To: <DBBPR08MB464664C773AFF2B57C3017A598C00@DBBPR08MB4646.eurprd08.prod.outlook.com>
Accept-Language: en-US
Content-Language: en-US
X-MS-Has-Attach:
X-MS-TNEF-Correlator:
dlp-product: dlpe-windows
dlp-reaction: no-action
dlp-version: 11.2.0.6
authentication-results: spf=none (sender IP is )
smtp.mailfrom=erik.g.carrillo@intel.com;
x-originating-ip: [192.55.52.217]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: 97d69d47-bb35-4f87-44fd-08d7dc0371cb
x-ms-traffictypediagnostic: SA0PR11MB4736:
x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr
x-ms-exchange-transport-forked: True
x-microsoft-antispam-prvs: <SA0PR11MB473658E9BC1CDC1825958A4EB9C00@SA0PR11MB4736.namprd11.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:8882;
x-forefront-prvs: 0367A50BB1
x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:SA0PR11MB4656.namprd11.prod.outlook.com; PTR:; CAT:NONE;
SFTY:;
SFS:(10019020)(376002)(396003)(39860400002)(366004)(346002)(136003)(5660300002)(76116006)(7696005)(186003)(4326008)(30864003)(26005)(66446008)(64756008)(66946007)(81166007)(2906002)(66476007)(66556008)(71200400001)(478600001)(9686003)(7416002)(110136005)(54906003)(15650500001)(52536014)(6506007)(55016002)(316002)(8936002)(53546011)(86362001)(33656002)(81156014)(8676002);
DIR:OUT; SFP:1102;
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: huKrKHmksbh6oJaHTIfelI6v/00Jf6DmyZ/48t6k+vhDuhtoJJy4KLRrjMCukpbNyPIlthFNspq9Gau58Jyz6ywj9fhZeU6RBy300EwHqFsd5dwhi+5+xMDjquAZHMHM7BCxwTs33z/jl2xgaz8aSJshbRgerkwkAycloSLK24GDkgRLrknbqE84N0N3EF8kRA/l1Hge/Sx2JZorFlPch+t5y9ew3ooaazzkUrQUp0kNoh6U7fpcXGAjb9TO1f62ZAVcJfoLwjsHj1rsbK6/096Q/38y62SOoV4TqeAQdZpSwRFeljDsaWHYR+oPPJxs09k1Fy3og/NRzSNclp9Ilei4twBwTaGoL3po6zcv9BNNpNi4qg1Oxolbpdk1ghZwjwHU/6YQx/+m5BpghiZK0KL4pPkCEwJf3h72xexxrpNl2eboVQ7GHiizxp1x/bAg
x-ms-exchange-antispam-messagedata: Snla3Jw6a0rsCwt5vijPLaIpCfQ0I0kZdQL/VP1ovwo9UDxeVbPA5CGgBO0kzrHU8kc6uJxbyWwx7D2dKBb7PxOs3pjnuOPZyyef2CCPXAaWXERT2eS/yo0sXWKB5qzFoT3t0Em7HuHGQ37dp3ZvMw==
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 97d69d47-bb35-4f87-44fd-08d7dc0371cb
X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Apr 2020 21:26:04.6382 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: FPd3D9LtyMQQLDg0QHhQ8gn83WYD+wu5iGddUoc4cKasJxzuLqpgs6JQXQTkx5Kg+8SIKjvhOe1mLZFUirgK868XJz/lwm7Yi2dfMuRxsxw=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4736
X-OriginatorOrg: intel.com
Subject: Re: [dpdk-dev] [PATCH 2/2] lib/timer: relax barrier for status
update
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.15
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
> -----Original Message-----
> From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Sent: Wednesday, April 8, 2020 4:16 PM
> To: Carrillo, Erik G <erik.g.carrillo@intel.com>; Phil Yang
> <Phil.Yang@arm.com>; rsanford@akamai.com; dev@dpdk.org
> Cc: david.marchand@redhat.com; Burakov, Anatoly
> <anatoly.burakov@intel.com>; thomas@monjalon.net; jerinj@marvell.com;
> hemant.agrawal@nxp.com; Gavin Hu <Gavin.Hu@arm.com>; nd
> <nd@arm.com>; Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>;
> nd <nd@arm.com>
> Subject: RE: [PATCH 2/2] lib/timer: relax barrier for status update
>=20
> <snip>
>=20
> > > Subject: [PATCH 2/2] lib/timer: relax barrier for status update
> > >
> > > Volatile has no ordering semantics. The rte_timer structure defines
> > > timer status as a volatile variable and uses the rte_r/wmb barrier
> > > to guarantee inter-thread visibility.
> > >
> > > This patch optimized the volatile operation with c11 atomic
> > > operations and one-way barrier to save the performance penalty.
> > > According to the timer_perf_autotest benchmarking results, this
> > > patch can uplift 10%~16% timer appending performance, 3%~20% timer
> > > resetting performance and 45% timer callbacks scheduling performance
> > > on aarch64 and no loss in performance for x86.
> > >
> > > Suggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > > Signed-off-by: Phil Yang <phil.yang@arm.com>
> > > Reviewed-by: Gavin Hu <gavin.hu@arm.com>
> >
> > Hi Phil,
> >
> > It seems like the consensus is to generally avoid replacing rte_atomic_=
*
> > interfaces with the GCC builtins directly. In other areas of DPDK tha=
t are
> > being patched, are the <std_atomic.h> C11 APIs going to be investigated=
?
> It
> > seems like that decision will apply here as well.
> Agree. The new APIs are going to be 1 to 1 mapped with the built-in intri=
nsics
> (the memory orderings used themselves will not change). We should go
> ahead with the review and conclude any issues. Once the decision is made
> on what APIs to use, we can submit the next version using the APIs decide=
d.
>=20
Thanks, Honnappa.
I have reviewed the memory orderings and I see no issues with them. I do =
have a question regarding a comment - I'll pose it inline:
> >
> > Thanks,
> > Erik
> >
> > > ---
> > > lib/librte_timer/rte_timer.c | 90
> > > +++++++++++++++++++++++++++++++----
> > > ---------
> > > lib/librte_timer/rte_timer.h | 2 +-
> > > 2 files changed, 65 insertions(+), 27 deletions(-)
> > >
> > > diff --git a/lib/librte_timer/rte_timer.c
> > > b/lib/librte_timer/rte_timer.c index 269e921..be0262d 100644
> > > --- a/lib/librte_timer/rte_timer.c
> > > +++ b/lib/librte_timer/rte_timer.c
> > > @@ -10,7 +10,6 @@
> > > #include <assert.h>
> > > #include <sys/queue.h>
> > >
> > > -#include <rte_atomic.h>
> > > #include <rte_common.h>
> > > #include <rte_cycles.h>
> > > #include <rte_eal_memconfig.h>
> > > @@ -218,7 +217,7 @@ rte_timer_init(struct rte_timer *tim)
> > >
> > > status.state =3D RTE_TIMER_STOP;
> > > status.owner =3D RTE_TIMER_NO_OWNER;
> > > - tim->status.u32 =3D status.u32;
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > __ATOMIC_RELAXED);
> > > }
> > >
> > > /*
> > > @@ -239,9 +238,9 @@ timer_set_config_state(struct rte_timer *tim,
> > >
> > > /* wait that the timer is in correct status before update,
> > > * and mark it as being configured */
> > > - while (success =3D=3D 0) {
> > > - prev_status.u32 =3D tim->status.u32;
> > > + prev_status.u32 =3D __atomic_load_n(&tim->status.u32,
> > > __ATOMIC_RELAXED);
> > >
> > > + while (success =3D=3D 0) {
> > > /* timer is running on another core
> > > * or ready to run on local core, exit
> > > */
> > > @@ -258,9 +257,20 @@ timer_set_config_state(struct rte_timer *tim,
> > > * mark it atomically as being configured */
> > > status.state =3D RTE_TIMER_CONFIG;
> > > status.owner =3D (int16_t)lcore_id;
> > > - success =3D rte_atomic32_cmpset(&tim->status.u32,
> > > - prev_status.u32,
> > > - status.u32);
> > > + /* If status is observed as RTE_TIMER_CONFIG earlier,
> > > + * that's not going to cause any issues because the
> > > + * pattern is read for status then read the other members.
I don't follow the above comment. What is meant by "earlier"?
Thanks,
Erik
> > > + * In one of the callers to timer_set_config_state
> > > + * (the __rte_timer_reset) we set other members to the
> > > + * structure (period, expire, f, arg) we want these
> > > + * changes to be observed after our change to status.
> > > + * So we need __ATOMIC_ACQUIRE here.
> > > + */
> > > + success =3D __atomic_compare_exchange_n(&tim-
> > > >status.u32,
> > > + &prev_status.u32,
> > > + status.u32, 0,
> > > + __ATOMIC_ACQUIRE,
> > > + __ATOMIC_RELAXED);
> > > }
> > >
> > > ret_prev_status->u32 =3D prev_status.u32; @@ -279,20 +289,27 @@
> > > timer_set_running_state(struct rte_timer *tim)
> > >
> > > /* wait that the timer is in correct status before update,
> > > * and mark it as running */
> > > - while (success =3D=3D 0) {
> > > - prev_status.u32 =3D tim->status.u32;
> > > + prev_status.u32 =3D __atomic_load_n(&tim->status.u32,
> > > __ATOMIC_RELAXED);
> > >
> > > + while (success =3D=3D 0) {
> > > /* timer is not pending anymore */
> > > if (prev_status.state !=3D RTE_TIMER_PENDING)
> > > return -1;
> > >
> > > /* here, we know that timer is stopped or pending,
> > > - * mark it atomically as being configured */
> > > + * mark it atomically as being running
> > > + */
> > > status.state =3D RTE_TIMER_RUNNING;
> > > status.owner =3D (int16_t)lcore_id;
> > > - success =3D rte_atomic32_cmpset(&tim->status.u32,
> > > - prev_status.u32,
> > > - status.u32);
> > > + /* RUNNING states are acting as locked states. If the
> > > + * timer is in RUNNING state, the state cannot be changed
> > > + * by other threads. So, we should use ACQUIRE here.
> > > + */
> > > + success =3D __atomic_compare_exchange_n(&tim-
> > > >status.u32,
> > > + &prev_status.u32,
> > > + status.u32, 0,
> > > + __ATOMIC_ACQUIRE,
> > > + __ATOMIC_RELAXED);
> > > }
> > >
> > > return 0;
> > > @@ -520,10 +537,12 @@ __rte_timer_reset(struct rte_timer *tim,
> > > uint64_t expire,
> > >
> > > /* update state: as we are in CONFIG state, only us can modify
> > > * the state so we don't need to use cmpset() here */
> > > - rte_wmb();
> > > status.state =3D RTE_TIMER_PENDING;
> > > status.owner =3D (int16_t)tim_lcore;
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory operations above
> > > + * the status update are observed before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > __ATOMIC_RELEASE);
> > >
> > > if (tim_lcore !=3D lcore_id || !local_is_locked)
> > > rte_spinlock_unlock(&priv_timer[tim_lcore].list_lock);
> > > @@ -600,10 +619,12 @@ __rte_timer_stop(struct rte_timer *tim, int
> > > local_is_locked,
> > > }
> > >
> > > /* mark timer as stopped */
> > > - rte_wmb();
> > > status.state =3D RTE_TIMER_STOP;
> > > status.owner =3D RTE_TIMER_NO_OWNER;
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory operations above
> > > + * the status update are observed before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > __ATOMIC_RELEASE);
> > >
> > > return 0;
> > > }
> > > @@ -637,7 +658,8 @@ rte_timer_stop_sync(struct rte_timer *tim) int
> > > rte_timer_pending(struct rte_timer *tim) {
> > > - return tim->status.state =3D=3D RTE_TIMER_PENDING;
> > > + return __atomic_load_n(&tim->status.state,
> > > + __ATOMIC_RELAXED) =3D=3D
> > > RTE_TIMER_PENDING;
> > > }
> > >
> > > /* must be called periodically, run all timer that expired */ @@
> > > -739,8
> > > +761,12 @@ __rte_timer_manage(struct rte_timer_data *timer_data)
> > > /* remove from done list and mark timer as stopped
> > */
> > > status.state =3D RTE_TIMER_STOP;
> > > status.owner =3D RTE_TIMER_NO_OWNER;
> > > - rte_wmb();
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory
> > > + * operations above the status update are observed
> > > + * before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > + __ATOMIC_RELEASE);
> > > }
> > > else {
> > > /* keep it in list and mark timer as pending */ @@ -
> > > 748,8 +774,12 @@ __rte_timer_manage(struct rte_timer_data
> *timer_data)
> > > status.state =3D RTE_TIMER_PENDING;
> > > __TIMER_STAT_ADD(priv_timer, pending, 1);
> > > status.owner =3D (int16_t)lcore_id;
> > > - rte_wmb();
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory
> > > + * operations above the status update are observed
> > > + * before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > + __ATOMIC_RELEASE);
> > > __rte_timer_reset(tim, tim->expire + tim->period,
> > > tim->period, lcore_id, tim->f, tim->arg, 1,
> > > timer_data);
> > > @@ -919,8 +949,12 @@ rte_timer_alt_manage(uint32_t timer_data_id,
> > > /* remove from done list and mark timer as stopped
> > */
> > > status.state =3D RTE_TIMER_STOP;
> > > status.owner =3D RTE_TIMER_NO_OWNER;
> > > - rte_wmb();
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory
> > > + * operations above the status update are observed
> > > + * before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > + __ATOMIC_RELEASE);
> > > } else {
> > > /* keep it in list and mark timer as pending */
> > > rte_spinlock_lock(
> > > @@ -928,8 +962,12 @@ rte_timer_alt_manage(uint32_t timer_data_id,
> > > status.state =3D RTE_TIMER_PENDING;
> > > __TIMER_STAT_ADD(data->priv_timer, pending, 1);
> > > status.owner =3D (int16_t)this_lcore;
> > > - rte_wmb();
> > > - tim->status.u32 =3D status.u32;
> > > + /* The "RELEASE" ordering guarantees the memory
> > > + * operations above the status update are observed
> > > + * before the update by all threads
> > > + */
> > > + __atomic_store_n(&tim->status.u32, status.u32,
> > > + __ATOMIC_RELEASE);
> > > __rte_timer_reset(tim, tim->expire + tim->period,
> > > tim->period, this_lcore, tim->f, tim->arg, 1,
> > > data);
> > > diff --git a/lib/librte_timer/rte_timer.h
> > > b/lib/librte_timer/rte_timer.h index c6b3d45..df533fa 100644
> > > --- a/lib/librte_timer/rte_timer.h
> > > +++ b/lib/librte_timer/rte_timer.h
> > > @@ -101,7 +101,7 @@ struct rte_timer {
> > > uint64_t expire; /**< Time when timer expire. */
> > > struct rte_timer *sl_next[MAX_SKIPLIST_DEPTH];
> > > - volatile union rte_timer_status status; /**< Status of timer. */
> > > + union rte_timer_status status; /**< Status of timer. */
> > > uint64_t period; /**< Period of timer (0 if not periodic). */
> > > rte_timer_cb_t f; /**< Callback function. */
> > > void *arg; /**< Argument to callback function. */
> > > --
> > > 2.7.4