From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D412C4372F; Wed, 20 Dec 2023 07:29:30 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9905C40279; Wed, 20 Dec 2023 07:29:30 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by mails.dpdk.org (Postfix) with ESMTP id 9B09A400EF for ; Wed, 20 Dec 2023 07:29:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703053769; x=1734589769; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=16fOwnf57LcZrj38768n0BFYIpsyJ1Zbo3kllcZMLRU=; b=bTzrzXurkGzYgev7IGdZDg7jM9vkPn3dT4VpaSSyO/isfNXiEJlLH2bF /uqGNJhzNMvFt1gIk54wfwA2+N6X8vrziRaRAkNlNQwWa0SUd9gEbAltd dZjjy4aJMCkAwU/zb9Ic/xN5SEyFHghEUTBuCDoWD7AP9nlQvh2sMrBMG cbF6NLMpvzcRQvInDlIo6F9YvO58xOlyO7M6KblbiWnADvM4WfMQX/Zpe bV8MCKc7WaZ2QaTYYh9zNYRP4fcwvHsQ+N1c8kydJq0QXFZ7q7PL2Q6/a aaTT0oVHpTmoHOjVPUOwMszYVhM9u3BLoHEqC6ifZXKH3c7+QjPCurriV Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="9232052" X-IronPort-AV: E=Sophos;i="6.04,290,1695711600"; d="scan'208";a="9232052" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2023 22:29:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10929"; a="805148335" X-IronPort-AV: E=Sophos;i="6.04,290,1695711600"; d="scan'208";a="805148335" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga008.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 19 Dec 2023 22:29:26 -0800 Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 19 Dec 2023 22:29:25 -0800 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Tue, 19 Dec 2023 22:29:25 -0800 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.169) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Tue, 19 Dec 2023 22:29:25 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Od+nQWjln4GhPk1qb6wftEJoEislBRgKBQks9DKA02TAF8WQKdw1105D1WPewUJmW/LdWl53RuXYd3BP/FEZZJ0BtrCqOBMhqNk/fZWz9Ducayo41sLFUsE9lPN1jZ7NShgGNcNla9ZktABMsGdTqDaN6AU5QlyEOtN2AQl4ZdNFu/oqo5L39M57iCFDyVU7rFEOzM+xYz1+qpDRH52jxEmJHgmRHHhyGjtFv7+PKZkIssHhwU78KDXtBajTwOx/7seH1Dd6gP2kZ2RMXTVE73Wfwo2AzJuvJZGGnabwpMb2YcyLlRAuojly0eu9SSbUVAB3vtuq0+/9zua/Z8JRSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=o8JP/ozOZihRWqQPUr0AnTF0J3WHJECYwRED94D3Ah0=; b=b3xjFtKId1R3ADK76qj9TJAiXoxETw5Smb4QkfQD9y9X3f0EKcG+X+DfcWheGBxcNkbodgYFUCp2VLJQ4s0X7tG6SjACWvajA3I56cooUn7Ld5WdkPjk8YZphQP9vCzmVDhoeyT7Afk1CxKebBNTb8ouG+2ZtsrjbP65DAEDDX+rWx+SgxNhvAPDAJcwJBHvA5C69ryE8oJXbaEHe3Ul4ysUuoUXCejn2xV3UiPiWuPt+poBAdOXMYLjNaeowZflyvWJ+BU0Hqn9EuwNOU7TqAlX/7waPgjKt/sdRTKme908l9tMzvGRsKm3SRlmkcghwyLyUff4f+qummtYoOso4g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from SA1PR11MB6613.namprd11.prod.outlook.com (2603:10b6:806:254::9) by IA1PR11MB7853.namprd11.prod.outlook.com (2603:10b6:208:3f7::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.38; Wed, 20 Dec 2023 06:29:18 +0000 Received: from SA1PR11MB6613.namprd11.prod.outlook.com ([fe80::a2fb:a414:62ba:bfbb]) by SA1PR11MB6613.namprd11.prod.outlook.com ([fe80::a2fb:a414:62ba:bfbb%4]) with mapi id 15.20.7113.016; Wed, 20 Dec 2023 06:29:17 +0000 From: "Su, Simei" To: Chuanyu Xue , "Lu, Wenzhuo" , "Zhang, Qi Z" , "Xing, Beilei" CC: "dev@dpdk.org" Subject: RE: [PATCH] net/e1000: support launchtime feature Thread-Topic: [PATCH] net/e1000: support launchtime feature Thread-Index: AQHaMSa05jg+eXAv1UiAlNWb6QLwv7CxppGQ Date: Wed, 20 Dec 2023 06:29:17 +0000 Message-ID: References: <20231217202040.478959-1-chuanyu.xue@uconn.edu> In-Reply-To: <20231217202040.478959-1-chuanyu.xue@uconn.edu> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SA1PR11MB6613:EE_|IA1PR11MB7853:EE_ x-ms-office365-filtering-correlation-id: 325680c0-b603-4409-3ce8-08dc0124fe4d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: juyZ41iDH59FnyNuw9/NEg3w6Y7OilBlRiJ/BUTKlTPLwVu0ovpjPZJMOVI6joHI3l24D85NkBK7A8Lg9TTaUf2dflyB6f0bKLb7eQ2bdKGavuhq3dPX+MSJf3NaQZEp/Njpp0bLxfySAFd4Hyu767svjOSroDeF438OXSowTsRgV+KtnetGnpPvTBXV9rJrnx9myf5LEoNeKMZ/RgpMjnDb3WToKFu6caOM2ieg39YZpuBoJfO4wFXghmqZY53xvPrPMiG4ul0wNnb+B10QfclvOqQd5YfNi0cI0suA20P8r6z3nZtrN0HPxEu0VQDDvQQL7IS54DzY1Gw5ICfrbYadDKNZkqTW1TfT2ZL2oBkFXCLJZrl+Rzbrhxqs1Ln/VuGO3z3pWMOqVzn8Or/MWFNGBSh8+c2UvQB+QOzKsziUY8aBGegoZnfTm21XWUUPM657kUi/PfZxqEaeb9twyAl3zQOhW1XB/9UW3S+ZiKBdRw7JaWE4xbWkCc3WV4kBUSdQUZuWqolP7IfXV1P2No22X9OTpmQynjG++qKkNBx3g2hgCNz73PfdvMDb0tNc2+kHUB8al1QOr5YloEQasFpvMloZcDKOVvuABbNuya3OHIVlRvBnJA1rpTreOO7i x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:SA1PR11MB6613.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(366004)(396003)(39860400002)(136003)(376002)(346002)(230922051799003)(1800799012)(64100799003)(186009)(451199024)(55016003)(38070700009)(82960400001)(110136005)(6636002)(316002)(296002)(86362001)(33656002)(26005)(122000001)(38100700002)(83380400001)(71200400001)(53546011)(9686003)(66446008)(478600001)(66556008)(7696005)(52536014)(2906002)(6506007)(66476007)(64756008)(66946007)(76116006)(5660300002)(4326008)(41300700001)(8936002)(8676002); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?1BdhDcqGmnVjExt4+Z7itjZ1gxVLSRv1inMrPhjA5jcel3maYblDXDpHY0UT?= =?us-ascii?Q?R6d9ZT7SYJ8nKKmxrVGKxLLwF28zCjIcyexZk/G6VA0g3fOrmUstXdFq4Fl0?= =?us-ascii?Q?LqpLs9xUI9b4gZtWvb/8ZNRYD/oGY3Sfnh1lRbj/2y/6p/v6TjFh+tBqemz4?= =?us-ascii?Q?d1/sA4yWYFqyUBp4RIpp1vR4b47JqtJBYUhMjfXftR8Q3Uulf/v9jeLxX/BS?= =?us-ascii?Q?GXvgYhhDibuejsQDvHdZPbcqlKSx7HC6ctJogRcIqEH5bxtoB3Psk5QYCdwz?= =?us-ascii?Q?2n5BmG2w1LIPXfCIDw319zJEBHvo5l07i3GoRBCJWgcl+r2CgQjwKysJSld1?= =?us-ascii?Q?q9qaHa09wHoYGfrTWc5dz3AkBc7E1uavRmEIH11/NVkU72JYJp5HIsqktb9q?= =?us-ascii?Q?MJWzTIaxRtekMc6upd5beeyV5xEUFFVOm3Xg6BMUF4K3OJ4k6sR5o+W046pG?= =?us-ascii?Q?VEMRNec3o+vnWjMaS4HOlJNSgLd9z3cPqIHCLrDvxQgfNjhQKL4BUrH4HWUs?= =?us-ascii?Q?J4Xve0o0j8k1Rl1aNxJqMiRVuE+wggA0YSTduvLAfX7dxIMXopQq5mo+rwRm?= =?us-ascii?Q?pMW7lA41FTuxzf8jSI+Dv+woOnia6mzMrMDPmhDwSRpiQFAASeQN3ZX2vSFV?= =?us-ascii?Q?yNe/IsQx6LaDdRxEb+fwcNFSZn4s7ZGnii9iHa/EysBQSrEsXE0RYN2w1YIg?= =?us-ascii?Q?chPnWNY+kl5GyTZcpzwzXhp7r1FAFGu3d81lVydzeeWKT2N0MiG/5ep/l0mu?= =?us-ascii?Q?NWaydBNTnBiqvlKgloHKqnwFQ7leRgJ8nct256IWRaf03k6QV5gHl01k65nt?= =?us-ascii?Q?g9W+JHdww+ykTi/j+3FyDjWlqEXekIObCHO1QciSucUEHPASobMeh6rSEffz?= =?us-ascii?Q?6hospiHhFb7eAolJ1HV8v8LvBMaCiyua9qcxSghjyBhRLMUXP0GsBke6VnUm?= =?us-ascii?Q?lAvWq3yEue7ZZP0UAalw4edVaVkP9BZxPygkCpKCPCqpI4iLJsHNeCm3tN+t?= =?us-ascii?Q?3vduRG6aDUDGE8roZNiWdWRHj6awYJGHi3CGf41Yo/HcJev1ZtVssK2Ay7pu?= =?us-ascii?Q?dJILFhWEy0AlqKBBoge2Bo/8Tw9ie79lWSFUAte8FW/LpL5x2UFwUFwzykVH?= =?us-ascii?Q?HUJlPx+IkckCZPRYG3gSzPiGSSDhZAyJpRl2p4S3YeYyn6skUuYfzGlbH3uA?= =?us-ascii?Q?p4X3LZO3iYh+SbTPXpyhO8lRLYtnpy42QkUfsOwZZJ3xumnjWTAHfqxv2YJ9?= =?us-ascii?Q?mss23vhXyTctS4LnYkECqtyd7wWNrQpJNvw4VQ4hLN2dJjWZ8tu6dviVSueE?= =?us-ascii?Q?8+Ca7VEuab/lYBbCSpRHyY7ieDx9SUkcOsuwjF5sevtcFBcwQ5WsaQn7GFmy?= =?us-ascii?Q?cNxNgQyPsUnYnXUBOndeDVQg4bbFWTO2RuHKmfOmisvuYpfX5IVfpli+4Ygf?= =?us-ascii?Q?VakWbPfi/MTUonrlxxy/1AVqniuW1mXtUT/jYiJGTACDHO257TX3MmM5vWuy?= =?us-ascii?Q?OF1Gutqi17thyX3s+maWGW8MgQ41I7i9OLylBRPsw937LwT1kC/pcP6evyTH?= =?us-ascii?Q?WMgRuy/F2+UOqLUb6zQ=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6613.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 325680c0-b603-4409-3ce8-08dc0124fe4d X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2023 06:29:17.6464 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: MJQMHNta1/QFt+yk68uAwKML28P5HljfOfHQi5IqaVFDxBvIVAw56s5m7vLRgOpFpVq4jwtlO2yED775cwxWuw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB7853 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi Chuanyu, > -----Original Message----- > From: Chuanyu Xue > Sent: Monday, December 18, 2023 4:21 AM > To: Lu, Wenzhuo ; Zhang, Qi Z > ; Xing, Beilei > Cc: dev@dpdk.org; Chuanyu Xue > Subject: [PATCH] net/e1000: support launchtime feature >=20 > Enable the time-based scheduled Tx of packets based on the > RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP flag. The launchtime defines > the packet transmission time based on PTP clock at MAC layer, which shoul= d > be set to the advanced transmit descriptor. >=20 > Signed-off-by: Chuanyu Xue > --- > drivers/net/e1000/base/e1000_regs.h | 1 + > drivers/net/e1000/e1000_ethdev.h | 3 ++ > drivers/net/e1000/igb_ethdev.c | 28 ++++++++++++++++++ > drivers/net/e1000/igb_rxtx.c | 44 ++++++++++++++++++++++++----- > 4 files changed, 69 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/net/e1000/base/e1000_regs.h > b/drivers/net/e1000/base/e1000_regs.h > index d44de59c29..092d9d71e6 100644 > --- a/drivers/net/e1000/base/e1000_regs.h > +++ b/drivers/net/e1000/base/e1000_regs.h > @@ -162,6 +162,7 @@ >=20 > /* QAV Tx mode control register */ > #define E1000_I210_TQAVCTRL 0x3570 > +#define E1000_I210_LAUNCH_OS0 0x3578 What does this register mean? >=20 > /* QAV Tx mode control register bitfields masks */ > /* QAV enable */ > diff --git a/drivers/net/e1000/e1000_ethdev.h > b/drivers/net/e1000/e1000_ethdev.h > index 718a9746ed..174f7aaf52 100644 > --- a/drivers/net/e1000/e1000_ethdev.h > +++ b/drivers/net/e1000/e1000_ethdev.h > @@ -382,6 +382,9 @@ extern struct igb_rss_filter_list igb_filter_rss_list= ; > TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem); extern struct > igb_flow_mem_list igb_flow_list; >=20 > +extern uint64_t igb_tx_timestamp_dynflag; extern int > +igb_tx_timestamp_dynfield_offset; > + > extern const struct rte_flow_ops igb_flow_ops; >=20 > /* > diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethde= v.c > index 8858f975f8..4d3d8ae30a 100644 > --- a/drivers/net/e1000/igb_ethdev.c > +++ b/drivers/net/e1000/igb_ethdev.c > @@ -223,6 +223,7 @@ static int igb_timesync_read_time(struct rte_eth_dev > *dev, > struct timespec *timestamp); > static int igb_timesync_write_time(struct rte_eth_dev *dev, > const struct timespec *timestamp); > +static int eth_igb_read_clock(__rte_unused struct rte_eth_dev *dev, > +uint64_t *clock); > static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev, > uint16_t queue_id); > static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev, @@ -31= 3,6 > +314,9 @@ static const struct rte_pci_id pci_id_igbvf_map[] =3D { > { .vendor_id =3D 0, /* sentinel */ }, > }; >=20 > +uint64_t igb_tx_timestamp_dynflag; > +int igb_tx_timestamp_dynfield_offset =3D -1; > + > static const struct rte_eth_desc_lim rx_desc_lim =3D { > .nb_max =3D E1000_MAX_RING_DESC, > .nb_min =3D E1000_MIN_RING_DESC, > @@ -389,6 +393,7 @@ static const struct eth_dev_ops eth_igb_ops =3D { > .timesync_adjust_time =3D igb_timesync_adjust_time, > .timesync_read_time =3D igb_timesync_read_time, > .timesync_write_time =3D igb_timesync_write_time, > + .read_clock =3D eth_igb_read_clock, > }; >=20 > /* > @@ -1198,6 +1203,7 @@ eth_igb_start(struct rte_eth_dev *dev) > struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); > struct rte_intr_handle *intr_handle =3D pci_dev->intr_handle; > int ret, mask; > + uint32_t tqavctrl; > uint32_t intr_vector =3D 0; > uint32_t ctrl_ext; > uint32_t *speeds; > @@ -1281,6 +1287,15 @@ eth_igb_start(struct rte_eth_dev *dev) > return ret; > } >=20 > + if (igb_tx_timestamp_dynflag > 0) { > + tqavctrl =3D E1000_READ_REG(hw, E1000_I210_TQAVCTRL); > + tqavctrl |=3D E1000_TQAVCTRL_MODE; > + tqavctrl |=3D E1000_TQAVCTRL_FETCH_ARB; /* Fetch the queue most > empty, no Round Robin*/ > + tqavctrl |=3D E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE; /* Enable > launch time */ In kernel driver, "E1000_TQAVCTRL_DATATRANTIM (BIT(9))" and "E1000_TQAVCTRL_FETCHTIME_DELTA (0xFFFF << 16)" are set, does it have some other intention here? > + E1000_WRITE_REG(hw, E1000_I210_TQAVCTRL, tqavctrl); > + E1000_WRITE_REG(hw, E1000_I210_LAUNCH_OS0, 1ULL << 31); /* > Set launch offset to default */ > + } > + > e1000_clear_hw_cntrs_base_generic(hw); >=20 > /* > @@ -4882,6 +4897,19 @@ igb_timesync_read_tx_timestamp(struct > rte_eth_dev *dev, > return 0; > } >=20 > +static int > +eth_igb_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t > +*clock) { > + uint64_t systime_cycles; > + struct e1000_adapter *adapter =3D dev->data->dev_private; > + > + systime_cycles =3D igb_read_systime_cyclecounter(dev); > + uint64_t ns =3D rte_timecounter_update(&adapter->systime_tc, > systime_cycles); Do you also run "ptp timesync" when testing this launchtime feature? > + *clock =3D ns; > + > + return 0; > +} > + > static int > eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused) { diff --g= it > a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index > 448c4b7d9d..e5da8e250d 100644 > --- a/drivers/net/e1000/igb_rxtx.c > +++ b/drivers/net/e1000/igb_rxtx.c > @@ -212,6 +212,9 @@ struct igb_tx_queue { > #define IGB_TSO_MAX_HDRLEN (512) > #define IGB_TSO_MAX_MSS (9216) >=20 > +/* Macro to compensate latency in launch time offloading*/ > +#define E1000_I210_LT_LATENCY 0x41F9 What does this value depend on? > + >=20 > /****************************************************************** > *** > * > * TX function > @@ -244,12 +247,13 @@ check_tso_para(uint64_t ol_req, union > igb_tx_offload ol_para) static inline void igbe_set_xmit_ctx(struct > igb_tx_queue* txq, > volatile struct e1000_adv_tx_context_desc *ctx_txd, > - uint64_t ol_flags, union igb_tx_offload tx_offload) > + uint64_t ol_flags, union igb_tx_offload tx_offload, uint64_t txtime) > { > uint32_t type_tucmd_mlhl; > uint32_t mss_l4len_idx; > uint32_t ctx_idx, ctx_curr; > uint32_t vlan_macip_lens; > + uint32_t launch_time; > union igb_tx_offload tx_offload_mask; >=20 > ctx_curr =3D txq->ctx_curr; > @@ -312,16 +316,25 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq, > } > } >=20 > - txq->ctx_cache[ctx_curr].flags =3D ol_flags; > - txq->ctx_cache[ctx_curr].tx_offload.data =3D > - tx_offload_mask.data & tx_offload.data; > - txq->ctx_cache[ctx_curr].tx_offload_mask =3D tx_offload_mask; > + if (!txtime) { > + txq->ctx_cache[ctx_curr].flags =3D ol_flags; > + txq->ctx_cache[ctx_curr].tx_offload.data =3D > + tx_offload_mask.data & tx_offload.data; > + txq->ctx_cache[ctx_curr].tx_offload_mask =3D tx_offload_mask; > + } >=20 > ctx_txd->type_tucmd_mlhl =3D rte_cpu_to_le_32(type_tucmd_mlhl); > vlan_macip_lens =3D (uint32_t)tx_offload.data; > ctx_txd->vlan_macip_lens =3D rte_cpu_to_le_32(vlan_macip_lens); > ctx_txd->mss_l4len_idx =3D rte_cpu_to_le_32(mss_l4len_idx); > ctx_txd->u.seqnum_seed =3D 0; > + > + if (txtime) { > + launch_time =3D (txtime - E1000_I210_LT_LATENCY) % NSEC_PER_SEC; > + ctx_txd->u.launch_time =3D rte_cpu_to_le_32(launch_time / 32); > + } else { > + ctx_txd->u.launch_time =3D 0; > + } > } >=20 > /* > @@ -400,6 +413,7 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf > **tx_pkts, > uint32_t new_ctx =3D 0; > uint32_t ctx =3D 0; > union igb_tx_offload tx_offload =3D {0}; > + uint64_t ts; >=20 > txq =3D tx_queue; > sw_ring =3D txq->sw_ring; > @@ -552,7 +566,12 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf > **tx_pkts, > txe->mbuf =3D NULL; > } >=20 > - igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload); > + if (igb_tx_timestamp_dynflag > 0) { > + ts =3D *RTE_MBUF_DYNFIELD(tx_pkt, > igb_tx_timestamp_dynfield_offset, uint64_t *); > + igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, > ts); > + } else { > + igbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, > 0); > + } >=20 > txe->last_id =3D tx_last; > tx_id =3D txe->next_id; > @@ -1464,7 +1483,8 @@ igb_get_tx_port_offloads_capa(struct rte_eth_dev > *dev) > RTE_ETH_TX_OFFLOAD_TCP_CKSUM | > RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | > RTE_ETH_TX_OFFLOAD_TCP_TSO | > - RTE_ETH_TX_OFFLOAD_MULTI_SEGS; > + RTE_ETH_TX_OFFLOAD_MULTI_SEGS | > + RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP; >=20 > return tx_offload_capa; > } > @@ -2579,9 +2599,11 @@ eth_igb_tx_init(struct rte_eth_dev *dev) { > struct e1000_hw *hw; > struct igb_tx_queue *txq; > + uint64_t offloads =3D dev->data->dev_conf.txmode.offloads; > uint32_t tctl; > uint32_t txdctl; > uint16_t i; > + int err; >=20 > hw =3D E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); >=20 > @@ -2612,6 +2634,14 @@ eth_igb_tx_init(struct rte_eth_dev *dev) > dev->data->tx_queue_state[i] =3D RTE_ETH_QUEUE_STATE_STARTED; > } >=20 > + if (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) { > + err =3D rte_mbuf_dyn_tx_timestamp_register( > + &igb_tx_timestamp_dynfield_offset, > + &igb_tx_timestamp_dynflag); > + if (err) > + PMD_DRV_LOG(ERR, "Failed to register tx timestamp dynamic > field"); > + } > + > /* Program the Transmit Control Register. */ > tctl =3D E1000_READ_REG(hw, E1000_TCTL); > tctl &=3D ~E1000_TCTL_CT; > -- > 2.25.1