RE: [PATCH v2 2/3] net/enic: add speed capabilities for newer models

["Hyong Youb Kim (hyonkim)" <hyonkim@cisco.com>]

> -----Original Message-----
> From: Ferruh Yigit <ferruh.yigit@amd.com>
> Sent: Thursday, August 8, 2024 5:51 PM
> To: Hyong Youb Kim (hyonkim) <hyonkim@cisco.com>
> Cc: dev@dpdk.org; John Daley (johndale) <johndale@cisco.com>
> Subject: Re: [PATCH v2 2/3] net/enic: add speed capabilities for newer models
> 
> On 8/8/2024 7:14 AM, Hyong Youb Kim wrote:
> > Add 1400/14000 and 15000 models to the speed_capa list.
> >
> 
> Do you want to introduce this new device variants in the driver guide?
> 
> Also does it makes sense to document new device model support in the
> release notes?
> 

Updated doc and release notes.

Thanks.
-Hyong

> > Signed-off-by: Hyong Youb Kim <hyonkim@cisco.com>
> > Reviewed-by: John Daley <johndale@cisco.com>
> > ---
> >  drivers/net/enic/enic_ethdev.c | 21 +++++++++++++++++++++
> >  1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/net/enic/enic_ethdev.c b/drivers/net/enic/enic_ethdev.c
> > index 5c967677fb..62c8751d09 100644
> > --- a/drivers/net/enic/enic_ethdev.c
> > +++ b/drivers/net/enic/enic_ethdev.c
> > @@ -62,6 +62,27 @@ static const struct vic_speed_capa {
> >  	{ 0x021a, RTE_ETH_LINK_SPEED_40G }, /* 1487 MLOM */
> >  	{ 0x024a, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G },
> /* 1495 PCIe */
> >  	{ 0x024b, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G },
> /* 1497 MLOM */
> > +	{ 0x02af, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G },
> /* 1467 MLOM */
> > +	{ 0x02b0, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G },
> /* 1477 MLOM */
> > +	{ 0x02cf, RTE_ETH_LINK_SPEED_25G }, /* 14425 MLOM */
> > +	{ 0x02d0, RTE_ETH_LINK_SPEED_25G }, /* 14825 Mezz */
> > +	{ 0x02db, RTE_ETH_LINK_SPEED_100G }, /* 15231 MLOM */
> > +	{ 0x02dc, RTE_ETH_LINK_SPEED_10G }, /* 15411 MLOM */
> > +	{ 0x02dd, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G |
> > +		  RTE_ETH_LINK_SPEED_50G }, /* 15428 MLOM */
> > +	{ 0x02de, RTE_ETH_LINK_SPEED_25G }, /* 15420 MLOM */
> > +	{ 0x02e8, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G |
> > +		  RTE_ETH_LINK_SPEED_200G}, /* 15238 MLOM */
> > +	{ 0x02e0, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G |
> > +		  RTE_ETH_LINK_SPEED_50G }, /* 15427 MLOM */
> > +	{ 0x02df, RTE_ETH_LINK_SPEED_50G | RTE_ETH_LINK_SPEED_100G },
> /* 15230 MLOM */
> > +	{ 0x02e1, RTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_50G },
> /* 15422 Mezz */
> > +	{ 0x02e4, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G |
> > +		  RTE_ETH_LINK_SPEED_200G }, /* 15235 PCIe */
> > +	{ 0x02f2, RTE_ETH_LINK_SPEED_10G | RTE_ETH_LINK_SPEED_25G |
> > +		  RTE_ETH_LINK_SPEED_50G }, /* 15425 PCIe */
> > +	{ 0x02f3, RTE_ETH_LINK_SPEED_40G | RTE_ETH_LINK_SPEED_100G |
> > +		  RTE_ETH_LINK_SPEED_200G }, /* 15237 MLOM */
> >  	{ 0, 0 }, /* End marker */
> >  };
> >