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Fri, 12 Dec 2025 10:39:31 +0000 From: "Loftus, Ciara" To: "Richardson, Bruce" CC: "dev@dpdk.org" Subject: RE: [PATCH 02/13] net/ice: use same Tx path across processes Thread-Topic: [PATCH 02/13] net/ice: use same Tx path across processes Thread-Index: AQHcaP7HB1PzzyAuQ0qEI/NoAiv07LUcU8MAgAGAaMA= Date: Fri, 12 Dec 2025 10:39:31 +0000 Message-ID: References: <20251209112652.963981-1-ciara.loftus@intel.com> <20251209112652.963981-3-ciara.loftus@intel.com> In-Reply-To: Accept-Language: en-IE, en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SJ5PPF6E320AF71:EE_|CY5PR11MB6211:EE_ x-ms-office365-filtering-correlation-id: 8b93f1b7-a795-4c08-49e5-08de396abc23 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; ARA:13230040|376014|366016|1800799024|38070700021; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ5PPF6E320AF71.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8b93f1b7-a795-4c08-49e5-08de396abc23 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Dec 2025 10:39:31.8834 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8nf+h4U2YgMnhF7I74N6a6FLWAFAN1vgxbYx0KtrDH1czWdJ7Fr0RP7kJJxUXrHCzvH+yZmNqcLatAhX9GN3Ig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR11MB6211 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org >=20 > On Tue, Dec 09, 2025 at 11:26:41AM +0000, Ciara Loftus wrote: > > In the interest of simplicity, let the primary process select the Tx > > path to be used by all processes using the given device. > > > > The many logs which report individual Tx path selections have been > > consolidated into one single log. > > > > Signed-off-by: Ciara Loftus > > --- > > drivers/net/intel/ice/ice_ethdev.c | 1 + > > drivers/net/intel/ice/ice_ethdev.h | 12 ++- > > drivers/net/intel/ice/ice_rxtx.c | 139 ++++++++++++++++------------- > > 3 files changed, 87 insertions(+), 65 deletions(-) > > > > diff --git a/drivers/net/intel/ice/ice_ethdev.c > b/drivers/net/intel/ice/ice_ethdev.c > > index c721d135f5..a805e78d03 100644 > > --- a/drivers/net/intel/ice/ice_ethdev.c > > +++ b/drivers/net/intel/ice/ice_ethdev.c > > @@ -3900,6 +3900,7 @@ ice_dev_configure(struct rte_eth_dev *dev) > > ad->tx_simple_allowed =3D true; > > > > ad->rx_func_type =3D ICE_RX_DEFAULT; > > + ad->tx_func_type =3D ICE_TX_DEFAULT; > > > > if (dev->data->dev_conf.rxmode.mq_mode & > RTE_ETH_MQ_RX_RSS_FLAG) > > dev->data->dev_conf.rxmode.offloads |=3D > RTE_ETH_RX_OFFLOAD_RSS_HASH; > > diff --git a/drivers/net/intel/ice/ice_ethdev.h > b/drivers/net/intel/ice/ice_ethdev.h > > index 72ed65f13b..0b8af339d1 100644 > > --- a/drivers/net/intel/ice/ice_ethdev.h > > +++ b/drivers/net/intel/ice/ice_ethdev.h > > @@ -208,6 +208,16 @@ enum ice_rx_func_type { > > ICE_RX_AVX512_SCATTERED_OFFLOAD, > > }; > > > > +enum ice_tx_func_type { > > + ICE_TX_DEFAULT, > > + ICE_TX_SIMPLE, > > + ICE_TX_SSE, > > + ICE_TX_AVX2, > > + ICE_TX_AVX2_OFFLOAD, > > + ICE_TX_AVX512, > > + ICE_TX_AVX512_OFFLOAD, > > +}; > > + > > struct ice_adapter; > > > > /** > > @@ -658,6 +668,7 @@ struct ice_adapter { > > bool tx_vec_allowed; >=20 > Can tx_vec_allowed by dropped at this point? In this driver I don't think so, as it's used during ice_tx_done_cleanup() = to select the appropriate cleanup function. If we were to remove it we would need to evaluate something like the following every time instead of using the bool: ice_tx_path_infos[ad->tx_func_type].features.simd_width >=3D RTE_VECT_SIMD_= 128 >=20 > > bool tx_simple_allowed; > > enum ice_rx_func_type rx_func_type; > > + enum ice_tx_func_type tx_func_type; > > /* ptype mapping table */ > > alignas(RTE_CACHE_LINE_MIN_SIZE) uint32_t > ptype_tbl[ICE_MAX_PKT_TYPE]; > > bool is_safe_mode; > > @@ -679,7 +690,6 @@ struct ice_adapter { > > /* Set bit if the engine is disabled */ > > unsigned long disabled_engine_mask; > > struct ice_parser *psr; > > - enum rte_vect_max_simd tx_simd_width; > > bool rx_vec_offload_support; > > }; > > > > diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/i= ce_rxtx.c > > index 74db0fbec9..f05ca83e5b 100644 > > --- a/drivers/net/intel/ice/ice_rxtx.c > > +++ b/drivers/net/intel/ice/ice_rxtx.c > > @@ -4091,6 +4091,44 @@ ice_prep_pkts(void *tx_queue, struct rte_mbuf > **tx_pkts, > > return i; > > } > > > > +static const struct { > > + eth_tx_burst_t pkt_burst; > > + const char *info; > > +} ice_tx_burst_infos[] =3D { > > + [ICE_TX_DEFAULT] =3D { > > + .pkt_burst =3D ice_xmit_pkts, > > + .info =3D "Scalar" > > + }, > > + [ICE_TX_SIMPLE] =3D { > > + .pkt_burst =3D ice_xmit_pkts_simple, > > + .info =3D "Scalar Simple" > > + }, > > +#ifdef RTE_ARCH_X86 > > + [ICE_TX_SSE] =3D { > > + .pkt_burst =3D ice_xmit_pkts_vec, > > + .info =3D "Vector SSE" > > + }, > > + [ICE_TX_AVX2] =3D { > > + .pkt_burst =3D ice_xmit_pkts_vec_avx2, > > + .info =3D "Vector AVX2" > > + }, > > + [ICE_TX_AVX2_OFFLOAD] =3D { > > + .pkt_burst =3D ice_xmit_pkts_vec_avx2_offload, > > + .info =3D "Offload Vector AVX2" > > + }, > > +#ifdef CC_AVX512_SUPPORT > > + [ICE_TX_AVX512] =3D { > > + .pkt_burst =3D ice_xmit_pkts_vec_avx512, > > + .info =3D "Vector AVX512" > > + }, > > + [ICE_TX_AVX512_OFFLOAD] =3D { > > + .pkt_burst =3D ice_xmit_pkts_vec_avx512_offload, > > + .info =3D "Offload Vector AVX512" > > + }, > > +#endif > > +#endif > > +}; > > + > > void __rte_cold > > ice_set_tx_function(struct rte_eth_dev *dev) > > { > > @@ -4101,74 +4139,58 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > struct ci_tx_queue *txq; > > int i; > > int tx_check_ret =3D -1; > > + enum rte_vect_max_simd tx_simd_width =3D > RTE_VECT_SIMD_DISABLED; > > > > - if (rte_eal_process_type() =3D=3D RTE_PROC_PRIMARY) { > > - ad->tx_simd_width =3D RTE_VECT_SIMD_DISABLED; > > - tx_check_ret =3D ice_tx_vec_dev_check(dev); > > - ad->tx_simd_width =3D ice_get_max_simd_bitwidth(); > > - if (tx_check_ret >=3D 0 && > > - rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_128) { > > - ad->tx_vec_allowed =3D true; > > - > > - if (ad->tx_simd_width < RTE_VECT_SIMD_256 && > > - tx_check_ret =3D=3D > ICE_VECTOR_OFFLOAD_PATH) > > - ad->tx_vec_allowed =3D false; > > - > > - if (ad->tx_vec_allowed) { > > - for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > > - txq =3D dev->data->tx_queues[i]; > > - if (txq && ice_txq_vec_setup(txq)) { > > - ad->tx_vec_allowed =3D false; > > - break; > > - } > > + /* The primary process selects the tx path for all processes. */ > > + if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) > > + goto out; > > + > > + tx_check_ret =3D ice_tx_vec_dev_check(dev); > > + tx_simd_width =3D ice_get_max_simd_bitwidth(); > > + if (tx_check_ret >=3D 0 && > > + rte_vect_get_max_simd_bitwidth() >=3D RTE_VECT_SIMD_128) > { > > + ad->tx_vec_allowed =3D true; > > + > > + if (tx_simd_width < RTE_VECT_SIMD_256 && > > + tx_check_ret =3D=3D ICE_VECTOR_OFFLOAD_PATH) > > + ad->tx_vec_allowed =3D false; > > + > > + if (ad->tx_vec_allowed) { > > + for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > > + txq =3D dev->data->tx_queues[i]; > > + if (txq && ice_txq_vec_setup(txq)) { > > + ad->tx_vec_allowed =3D false; > > + break; > > } > > } > > - } else { > > - ad->tx_vec_allowed =3D false; > > } > > + } else { > > + ad->tx_vec_allowed =3D false; > > } > > > > if (ad->tx_vec_allowed) { > > dev->tx_pkt_prepare =3D rte_eth_tx_pkt_prepare_dummy; > > - if (ad->tx_simd_width =3D=3D RTE_VECT_SIMD_512) { > > + if (tx_simd_width =3D=3D RTE_VECT_SIMD_512) { > > #ifdef CC_AVX512_SUPPORT > > if (tx_check_ret =3D=3D ICE_VECTOR_OFFLOAD_PATH) { > > - PMD_DRV_LOG(NOTICE, > > - "Using AVX512 OFFLOAD Vector Tx > (port %d).", > > - dev->data->port_id); > > - dev->tx_pkt_burst =3D > > - ice_xmit_pkts_vec_avx512_offload; > > + ad->tx_func_type =3D > ICE_TX_AVX512_OFFLOAD; > > dev->tx_pkt_prepare =3D ice_prep_pkts; > > } else { > > - PMD_DRV_LOG(NOTICE, > > - "Using AVX512 Vector Tx (port > %d).", > > - dev->data->port_id); > > - dev->tx_pkt_burst =3D > ice_xmit_pkts_vec_avx512; > > + ad->tx_func_type =3D ICE_TX_AVX512; > > } > > #endif > > } else { > > if (tx_check_ret =3D=3D ICE_VECTOR_OFFLOAD_PATH) { > > - PMD_DRV_LOG(NOTICE, > > - "Using AVX2 OFFLOAD Vector Tx > (port %d).", > > - dev->data->port_id); > > - dev->tx_pkt_burst =3D > > - ice_xmit_pkts_vec_avx2_offload; > > + ad->tx_func_type =3D ICE_TX_AVX2_OFFLOAD; > > dev->tx_pkt_prepare =3D ice_prep_pkts; > > } else { > > - PMD_DRV_LOG(DEBUG, "Using %sVector Tx > (port %d).", > > - ad->tx_simd_width =3D=3D > RTE_VECT_SIMD_256 ? "avx2 " : "", > > - dev->data->port_id); > > - dev->tx_pkt_burst =3D ad->tx_simd_width =3D=3D > RTE_VECT_SIMD_256 ? > > - ice_xmit_pkts_vec_avx2 : > > - ice_xmit_pkts_vec; > > + ad->tx_func_type =3D tx_simd_width =3D=3D > RTE_VECT_SIMD_256 ? > > + ICE_TX_AVX2 : > > + ICE_TX_SSE; > > } > > } > > > > - if (mbuf_check) { > > - ad->tx_pkt_burst =3D dev->tx_pkt_burst; > > - dev->tx_pkt_burst =3D ice_xmit_pkts_check; > > - } > > - return; > > + goto out; > > } > > #endif > > > > @@ -4186,24 +4208,13 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > ad->tx_pkt_burst =3D dev->tx_pkt_burst; > > dev->tx_pkt_burst =3D ice_xmit_pkts_check; > > } > > -} > > > > -static const struct { > > - eth_tx_burst_t pkt_burst; > > - const char *info; > > -} ice_tx_burst_infos[] =3D { > > - { ice_xmit_pkts_simple, "Scalar Simple" }, > > - { ice_xmit_pkts, "Scalar" }, > > -#ifdef RTE_ARCH_X86 > > -#ifdef CC_AVX512_SUPPORT > > - { ice_xmit_pkts_vec_avx512, "Vector AVX512" }, > > - { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" }, > > -#endif > > - { ice_xmit_pkts_vec_avx2, "Vector AVX2" }, > > - { ice_xmit_pkts_vec_avx2_offload, "Offload Vector AVX2" }, > > - { ice_xmit_pkts_vec, "Vector SSE" }, > > -#endif > > -}; >=20 > Looking at the code with this patch applied, I think there may be an issu= e > with the scalar case in this version. At line 4197 we have a block which > assigns a value to tx_pkt_burst and tx_burst_prepare, but does not assign= a > value to the tx_func_type values. That means when it falls through into t= he > "out" section, the function point for pkt_burst get overwritten. This should be fixed in the v2. >=20 > > +out: > > + dev->tx_pkt_burst =3D mbuf_check ? ice_xmit_pkts_check : > > + ice_tx_burst_infos[ad- > >tx_func_type].pkt_burst; > > + PMD_DRV_LOG(NOTICE, "Using %s (port %d).", > > + ice_tx_burst_infos[ad->tx_func_type].info, dev->data- > >port_id); > > +} > > > > int > > ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t > queue_id, > > -- > > 2.43.0 > >