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Thu, 9 Jan 2020 00:48:58 +0000 Received: from SN6PR11MB2558.namprd11.prod.outlook.com ([fe80::4d86:362a:13c3:8386]) by SN6PR11MB2558.namprd11.prod.outlook.com ([fe80::4d86:362a:13c3:8386%7]) with mapi id 15.20.2623.008; Thu, 9 Jan 2020 00:48:57 +0000 From: "Ananyev, Konstantin" To: Honnappa Nagarahalli , "olivier.matz@6wind.com" , "sthemmin@microsoft.com" , "jerinj@marvell.com" , "Richardson, Bruce" , "david.marchand@redhat.com" , "pbhagavatula@marvell.com" CC: "dev@dpdk.org" , Dharmik Thakkar , Ruifeng Wang , Gavin Hu , nd , nd Thread-Topic: [PATCH v7 02/17] lib/ring: apis to support configurable element size Thread-Index: AQHVtvB22uIJex5+gEyRiFOc8yhYEqfXpo/wgAckGwCAAAcRgIAAR9qggABU2wCAAAOEAIAA9tKAgAA+MMCAAOURgIAAEbOg Date: Thu, 9 Jan 2020 00:48:57 +0000 Message-ID: References: <20190906190510.11146-1-honnappa.nagarahalli@arm.com> <20191220044524.32910-1-honnappa.nagarahalli@arm.com> <20191220044524.32910-3-honnappa.nagarahalli@arm.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTU3ZDBkZTMtMDNjOC00NTA5LWExZTQtN2FhNTZjMWY4ODk5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoia0RnenN3U3lLVmQ0R0xXMHVjSFNCRk8rRk1zQVlvWldReW9rcUtMQTYzOFlhbFMrR2NGSlVZYjFPR284UjZIaCJ9 dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 x-ctpclassification: CTP_NT authentication-results: spf=none (sender IP is ) smtp.mailfrom=konstantin.ananyev@intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a2ffd90a-ba1e-4807-90e1-08d7949db5f6 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2020 00:48:57.8216 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NgjSwLESkWbv426cekMrYeAPWkLVJt3NY3zS3FRdh9fyLzPjJgf5kl8g8gzl7a15w3LBu5Cn1O9YJe0aFUKZ9qMQNomkqNmLMJRrbJlDURc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2735 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v7 02/17] lib/ring: apis to support configurable element size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > > > > > > > > + > > > > > > > > > > +static __rte_always_inline void > > > > > > > > > > +enqueue_elems_128(struct rte_ring *r, uint32_t > > > > > > > > > > +prod_head, const void *obj_table, uint32_t n) { > > > > > > > > > > +unsigned int i; const uint32_t size =3D > > > > > > > > > > +r->size; uint32_t idx =3D prod_head & r->mask; > > > > > > > > > > +r->__uint128_t > > > > > > > > > > +*ring =3D (__uint128_t *)&r[1]; const __uint128_t *obj= =3D > > > > > > > > > > +(const __uint128_t *)obj_table; if (likely(idx + n < > > > > > > > > > > +size)) { for (i =3D 0; i < (n & ~0x1); i +=3D 2, idx += =3D 2) > > > > > > > > > > +{ ring[idx] =3D obj[i]; ring[idx + 1] =3D obj[i + 1]; > > > > > > > > > > > > > > > > > > > > > > > > > > > AFAIK, that implies 16B aligned obj_table... > > > > > > > > > Would it always be the case? > > > > > > > > I am not sure from the compiler perspective. > > > > > > > > At least on Arm architecture, unaligned access (address tha= t > > > > > > > > is accessed is not aligned to the size of the data element > > > > > > > > being > > > > > > > > accessed) will result in faults or require additional cycle= s. > > > > > > > > So, aligning on > > > > > > 16B should be fine. > > > > > > > Further, I would be changing this to use 'rte_int128_t' as > > > > > > > '__uint128_t' is > > > > > > not defined on 32b systems. > > > > > > > > > > > > What I am trying to say: with this code we imply new requiremen= t > > > > > > for elems > > > > > The only existing use case in DPDK for 16B is the event ring. The > > > > > event ring > > > > already does similar kind of copy (using 'struct rte_event'). > > > > > So, there is no change in expectations for event ring. > > > > > For future code, I think this expectation should be fine since it > > > > > allows for > > > > optimal code. > > > > > > > > > > > in the ring: when sizeof(elem)=3D=3D16 it's alignment also has = to be > > > > > > at least > > > > 16. > > > > > > Which from my perspective is not ideal. > > > > > Any reasoning? > > > > > > > > New implicit requirement and inconsistency. > > > > Code like that: > > > > > > > > struct ring_elem {uint64_t a, b;}; > > > > .... > > > > struct ring_elem elem; > > > > rte_ring_dequeue_elem(ring, &elem, sizeof(elem)); > > > > > > > > might cause a crash. > > > The alignment here is 8B. Assuming that instructions generated will > > > require 16B alignment, it will result in a crash, if configured to ge= nerate > > exception. > > > But, these instructions are not atomic instructions. At least on > > > aarch64, unaligned access will not result in an exception for non-ato= mic > > loads/stores. I believe it is the same behavior for x86 as well. > > > > On IA, there are 2 types of 16B load/store instructions: aligned and un= aligned. > > Aligned are a bit faster, but will cause an exception if used on non 16= B aligned > > address. > > As you using uint128_t * compiler will assume that both src and dst are= 16B > > aligned and might generate code with aligned instructions. > Ok, looking at few articles, I read that if the address is aligned, the u= naligned instructions do not incur the penalty. Is this understanding > correct? Yes, from my experience the difference is negligible. >=20 > I see 2 solutions here: > 1) We can switch this copy to use uint32_t pointer. It would still allow = the compiler to generate (unaligned) instructions for up to 256b > load/store. The 2 multiplications (to normalize the index and the size of= copy) can use shifts. This should make it safer. If one wants > performance, they can align the obj table to 16B (the ring itself is alre= ady aligned on the cache line boundary). Sounds good to me. >=20 > 2) Considering that performance is paramount, we could document that the = obj table needs to be aligned on 16B boundary. This would > affect event dev (if we go ahead with replacing the event ring implementa= tion) significantly. I don't think perf difference would be that significant to justify such con= straint. I am in favor of #1. =20 > Note that we have to do the same thing for 64b elements as well. I don't mind to have one unified copy procedure, which would always use 32b= it elems, but AFAIK, on IA there is no such limitation for 64bit load/stores. >=20 > > > > > > > > > While exactly the same code with: > > > > > > > > struct ring_elem {uint64_t a, b, c;}; OR struct ring_elem {uint64_t > > > > a, b, c, d;}; > > > > > > > > will work ok. > > > The alignment for these structures is still 8B. Are you saying this > > > will work because these will be copied using pointer to uint32_t (who= se > > alignment is 4B)? > > > > Yes, as we doing uint32_t copies, compiler can't assume the data will b= e 16B > > aligned and will use unaligned instructions. > > > > > > > > > > > > > > > > > > > > Note that for elem sizes > 16 (24, 32), there is no such constr= aint. > > > > > The rest of them need to be aligned on 4B boundary. However, this > > > > > should > > > > not affect the existing code. > > > > > The code for 8B and 16B is kept as is to ensure the performance i= s > > > > > not > > > > affected for the existing code. > > >