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Tue, 20 Oct 2020 14:02:42 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH v2 11/22] event/dlb2: add port setup Thread-Index: AQHWpLIUFtkYg8cn+kSc48BB9pcnDamfr4Dw Date: Tue, 20 Oct 2020 14:02:42 +0000 Message-ID: References: <1599855987-25976-2-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-1-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-12-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1602958879-8558-12-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [68.203.30.51] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: de104d3a-ea54-4083-ea26-08d87500d035 x-ms-traffictypediagnostic: SA2PR11MB5097: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3513; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: de104d3a-ea54-4083-ea26-08d87500d035 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Oct 2020 14:02:42.4890 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NQNaQ/HZIuUPm53DEjbdd72rxGPtEyHZ3cpjmapXGUJX3UyAOUe4ixS4TrhitBEKUGOdM+GyEwE8BilcxCvL4w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB5097 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 11/22] event/dlb2: add port setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" [...] > +static int > +dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle, > + struct dlb2_create_ldb_port_args *cfg, > + enum dlb2_cq_poll_modes poll_mode) > +{ > + struct dlb2_dev *dlb2_dev =3D (struct dlb2_dev *)handle->pf_dev; > + struct dlb2_cmd_response response =3D {0}; > + struct dlb2_port_memory port_memory; > + int ret, cq_alloc_depth; > + uint8_t *port_base; > + const struct rte_memzone *mz; > + int alloc_sz, qe_sz; > + phys_addr_t cq_base; > + phys_addr_t pp_base; > + int is_dir =3D false; > + > + DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__); > + > + if (poll_mode =3D=3D DLB2_CQ_POLL_MODE_STD) > + qe_sz =3D sizeof(struct dlb2_dequeue_qe); > + else > + qe_sz =3D RTE_CACHE_LINE_SIZE; > + > + /* Calculate the port memory required, and round up to the nearest > + * cache line. > + */ > + cq_alloc_depth =3D RTE_MAX(cfg->cq_depth, > DLB2_MIN_HARDWARE_CQ_DEPTH); > + alloc_sz =3D cq_alloc_depth * qe_sz; > + alloc_sz =3D RTE_CACHE_LINE_ROUNDUP(alloc_sz); > + > + port_base =3D dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz, > + PAGE_SIZE); > + if (port_base =3D=3D NULL) > + return -ENOMEM; > + > + /* Lock the page in memory */ > + ret =3D rte_mem_lock_page(port_base); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device > i/o\n"); > + goto create_port_err; > + } > + > + Nit: extra newline > + memset(port_base, 0, alloc_sz); > + > + ret =3D dlb2_pf_create_ldb_port(&dlb2_dev->hw, > + handle->domain_id, > + cfg, > + cq_base, > + &response); > + if (ret) > + goto create_port_err; > + > + pp_base =3D (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir); > + dlb2_port[response.id][DLB2_LDB_PORT].pp_addr =3D > + (void *)(pp_base + (PAGE_SIZE * response.id)); > + > + dlb2_port[response.id][DLB2_LDB_PORT].cq_base =3D (void *)(port_base); > + memset(&port_memory, 0, sizeof(port_memory)); > + > + dlb2_port[response.id][DLB2_LDB_PORT].mz =3D mz; > + > + dlb2_list_init_head(&port_memory.list); > + > + cfg->response =3D response; > + > + return 0; > + > +create_port_err: > + > + rte_free(port_base); This should be "rte_memzone_free(mz);" > + > + DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=3D%d\n", > + __func__, ret); > + return ret; > +} > + > +static int > +dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle, > + struct dlb2_create_dir_port_args *cfg, > + enum dlb2_cq_poll_modes poll_mode) > +{ > + struct dlb2_dev *dlb2_dev =3D (struct dlb2_dev *)handle->pf_dev; > + struct dlb2_cmd_response response =3D {0}; > + struct dlb2_port_memory port_memory; > + int ret; > + uint8_t *port_base; > + const struct rte_memzone *mz; > + int alloc_sz, qe_sz; > + phys_addr_t cq_base; > + phys_addr_t pp_base; > + int is_dir =3D true; > + > + DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__); > + > + if (poll_mode =3D=3D DLB2_CQ_POLL_MODE_STD) > + qe_sz =3D sizeof(struct dlb2_dequeue_qe); > + else > + qe_sz =3D RTE_CACHE_LINE_SIZE; > + > + /* Calculate the port memory required, and round up to the nearest > + * cache line. > + */ > + alloc_sz =3D cfg->cq_depth * qe_sz; > + alloc_sz =3D RTE_CACHE_LINE_ROUNDUP(alloc_sz); > + > + port_base =3D dlb2_alloc_coherent_aligned(&mz, &cq_base, alloc_sz, > + PAGE_SIZE); > + if (port_base =3D=3D NULL) > + return -ENOMEM; > + > + /* Lock the page in memory */ > + ret =3D rte_mem_lock_page(port_base); > + if (ret < 0) { > + DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device > i/o\n"); > + goto create_port_err; > + } > + > + memset(port_base, 0, alloc_sz); > + > + ret =3D dlb2_pf_create_dir_port(&dlb2_dev->hw, > + handle->domain_id, > + cfg, > + cq_base, > + &response); > + if (ret) > + goto create_port_err; > + > + pp_base =3D (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir); > + dlb2_port[response.id][DLB2_DIR_PORT].pp_addr =3D > + (void *)(pp_base + (PAGE_SIZE * response.id)); > + > + dlb2_port[response.id][DLB2_DIR_PORT].cq_base =3D > + (void *)(port_base); > + memset(&port_memory, 0, sizeof(port_memory)); > + > + dlb2_port[response.id][DLB2_DIR_PORT].mz =3D mz; > + > + dlb2_list_init_head(&port_memory.list); > + > + cfg->response =3D response; > + > + return 0; > + > +create_port_err: > + > + rte_free(port_base); Ditto Thanks, Gage