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Wed, 7 Oct 2020 19:26:33 +0000 Received: from SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a]) by SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a%4]) with mapi id 15.20.3455.021; Wed, 7 Oct 2020 19:26:33 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH 10/22] event/dlb2: add queue setup Thread-Index: AQHWiHpY/vNqwPsnmUWMbmuTo2JKmqmMrLVA Date: Wed, 7 Oct 2020 19:26:33 +0000 Message-ID: References: <1599855987-25976-1-git-send-email-timothy.mcdaniel@intel.com> <1599855987-25976-11-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1599855987-25976-11-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 7ahLHXrhOqlCNDzs4N+UUboTvMv517x1dAnldISRqCi4Fq2Pz0OZYOZSSLIuxChfkS3bO26SQlBxeRR5B7r7UxhzC+3GDf4DFQv+77pLXwMthNkG+eUSLdA0Xm7MmLBC2onb/RZpAMeS+ovJQNGJab0RjM9+iWNdg/QVoel6NFXQwPf0muQu2hFjzUAGn0NhfrxCaiO0Gsv7pzAG8p2hcwuEPtUSruE7WoZycCkAsYkdDSN7Ggh5yRTnGk1XXBTCyLFmr0XGwyG2QtuidegNFUsAZalD54wo6mG4IUXvx7epaor8mD05prLqUb47kTES5M5trAQppzYWlLM0d3kMD/Qh6S10iOOMWHioZs3mkPDntIUYL1cjsAF72GFtfXJvcTq118JSAOBHsBY2VZQ33qMUzayXqwP9alBpXyNxr0bJuQuzTG7bVZEJDTY73T4vNYBjKK/pYoJlRtCeKWNu5yxyUZturvbsljfMeXknig1bWVRLzqSDKiccQyjpnW8y4dxmgOKNK8kZwTYSeuZVwJ5Kb3E47S9QBq8idfis3hKmCETXrXhpp0MsvacydxT7VT7I4yEICy492IG65b/VGqD2MGhy8WGLEbtwgZzGSFEB0ViT9kbefmNTjflACbrQ6e8eTZQlxtDXxNA3Ppj1JA== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9249b237-dea3-497c-5358-08d86af6e6b6 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Oct 2020 19:26:33.6993 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: PwbRRxw4qmNgYb3wPzHgiT0yBHpGnBEv+yMhH6BSWVnDZniByURbW9/EeL31y0gIvdL56OGaU9SCwTGpFIK7kw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR11MB4639 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 10/22] event/dlb2: add queue setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > +static int > +dlb2_eventdev_ldb_queue_setup(struct rte_eventdev *dev, > + struct dlb2_eventdev_queue *ev_queue, > + const struct rte_event_queue_conf *queue_conf) > +{ > + struct dlb2_eventdev *dlb2 =3D dlb2_pmd_priv(dev); > + int32_t qm_qid; > + > + if (queue_conf->nb_atomic_order_sequences) > + dlb2_program_sn_allocation(dlb2, queue_conf); > + > + qm_qid =3D dlb2_hw_create_ldb_queue(dlb2, > + ev_queue, > + queue_conf); Nit: this can fit on one line Thanks, Gage