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Tue, 20 Oct 2020 20:06:53 +0000 Received: from SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a]) by SN6PR11MB2574.namprd11.prod.outlook.com ([fe80::902d:8f85:ea05:a7a%4]) with mapi id 15.20.3477.028; Tue, 20 Oct 2020 20:06:53 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH v5 16/22] event/dlb: add dequeue and its burst variants Thread-Index: AQHWpLgSL0G3PYQjCUiffHMJX5/iWamg7vPA Date: Tue, 20 Oct 2020 20:06:53 +0000 Message-ID: References: <1596138614-17409-2-git-send-email-timothy.mcdaniel@intel.com> <1602961456-17392-1-git-send-email-timothy.mcdaniel@intel.com> <1602961456-17392-17-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1602961456-17392-17-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; 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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: fvQpYPqdO3vD5T31HU8r3RIOdBnyGu6UvL1T0FEH4JBiA+vdaMZGt7q+k+3VqXTh5CO9YALebbGIUqrpLf73v0XLtAzhnzD5aDVaHAsyunFprXcP1jswU6UJwce71fzNo+EWEZ1absgOVRbYYAVhetKYIF7TdLvKfnXOeb8ye2i5Ureq8NDvG+MYij6ATGtdWCoNwPLt1NslYYio2gouaOgkCmb8Yd3h2VnQdfXdxrWUdOdDcxbHSZ/CB15zTvggcSuK/n++gKIK6IzOSclbTUzw77zKaLoMZJzKVZC+0GRQ+RU3Lk8OtGbEfN5CRbbWj8GeekZ0C4vI4rZHtI5KISWEPtFGstfisfrJitu8A4BQtX1pet8NmGchjxnyrz3N5K2Xtp5tJ5uG+s0nZSszyv5BJbJX0KWw4LlQc46LXCrWpNnMLOSKdgWhcoi38TbFKzgXMVLjeJ82FF6omatfdVNRMEzvVO1xsGKYyY1YqW1TMevs8w5nBxVOYNOAm2XNcGIflAxsda8oLnSNWuB7JwuSxnIL+1Ojjn8GRJyuut5Do9Vp0jZ027upO53Z8wGWuD0+MoXRGyj93LxHDt+2GHPL1j2zrQEePCwLuaUYc9obQ0PAqCiBuCuGjr4NkmWTqTtnvBMgTxQWni5jcKN64g== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 70bfbf49-d84c-4280-5862-08d87533b085 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Oct 2020 20:06:53.6916 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 12oYQ1SiVEyuN5xAEGr74J3O9i93ZYdDeaSPwK9pC71FgxNi9WSKUhYmhTGM6TxqqOqvK/g2nkvL/YzrmxEu4A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB4937 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v5 16/22] event/dlb: add dequeue and its burst variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Saturday, October 17, 2020 2:04 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH v5 16/22] event/dlb: add dequeue and its burst variants >=20 > Add support for dequeue, dequeue_burst, ... >=20 > DLB does not currently support interrupts, but instead uses > umonitor/umwait if supported by the processor. This allows > the software to monitor and wait on writes to a cache-line. >=20 > DLB supports normal and sparse cq mode. In normal mode the > hardware will pack 4 QEs into each cache line. In sparse cq > mode, the hardware will only populate one QE per cache line. > Software must be aware of the cq mode, and take the appropriate > actions, based on the mode. >=20 > Signed-off-by: Timothy McDaniel Reviewed-by: Gage Eads Thanks, Gage