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Tue, 20 Oct 2020 14:04:41 +0000 From: "Eads, Gage" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Van Haaren, Harry" , "jerinj@marvell.com" Thread-Topic: [PATCH v2 16/22] event/dlb2: add dequeue and its burst variants Thread-Index: AQHWpLIXRYMhJ4OsZEeVdlW6pzbRsamggTVA Date: Tue, 20 Oct 2020 14:04:41 +0000 Message-ID: References: <1599855987-25976-2-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-1-git-send-email-timothy.mcdaniel@intel.com> <1602958879-8558-17-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1602958879-8558-17-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [68.203.30.51] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a5c17d2f-f1f8-41b7-061c-08d8750116eb x-ms-traffictypediagnostic: SA2PR11MB5100: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2574.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a5c17d2f-f1f8-41b7-061c-08d8750116eb X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Oct 2020 14:04:41.1214 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 6RFXEQBiFHTHsYKkgjEGz8gDXKTeMjuksxB9iOv4/QIs5Ob/aA7l1xUCHu05wmUsqogdt9hWHYjWtQNkdiZeJA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB5100 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v2 16/22] event/dlb2: add dequeue and its burst variants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: McDaniel, Timothy > Sent: Saturday, October 17, 2020 1:21 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com > Subject: [PATCH v2 16/22] event/dlb2: add dequeue and its burst variants >=20 > Add support for dequeue, dequeue_burst, ... >=20 > DLB2 does not currently support interrupts, but instead use > umonitor/umwait if supported by the processor. This allows > the software to monitor and wait on writes to a cache-line. >=20 > DLB2 supports normal and sparse cq mode. In normal mode the > hardware will pack 4 QEs into each cache line. In sparse cq > mode, the hardware will only populate one QE per cache line. > Software must be aware of the cq mode, and take the appropriate > actions, based on the mode. >=20 > Signed-off-by: Timothy McDaniel Reviewed-by: Gage Eads Thanks, Gage