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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB2829.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 32c20b03-3785-43fd-e6c5-08d82a2b0f21 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2020 08:26:09.7166 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WXuXgxmdtA44bHC+KFrmQ6lRtFt1HY4JKYj4svHbNMHqfC8E0vtqjctLivaZMOhcOXYStYE6uFk99Kj/39TU+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR11MB2830 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH V4 4/4] net/i40e: FDIR update rate optimization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Best Regards, Sun, Chenmin > -----Original Message----- > From: Wu, Jingjing > Sent: Thursday, July 16, 2020 9:57 PM > To: Sun, Chenmin ; Zhang, Qi Z > ; Xing, Beilei ; Wang, Haiyu= e > > Cc: dev@dpdk.org > Subject: RE: [PATCH V4 4/4] net/i40e: FDIR update rate optimization >=20 >=20 > [...] >=20 > > +static inline unsigned char * > > +i40e_find_available_buffer(struct rte_eth_dev *dev) { > > + struct i40e_pf *pf =3D I40E_DEV_PRIVATE_TO_PF(dev->data- > >dev_private); > > + struct i40e_fdir_info *fdir_info =3D &pf->fdir; > > + struct i40e_tx_queue *txq =3D pf->fdir.txq; > > + volatile struct i40e_tx_desc *txdp =3D &txq->tx_ring[txq->tx_tail + 1= ]; > > + uint32_t i; > > + > > + /* no available buffer > > + * search for more available buffers from the current > > + * descriptor, until an unavailable one > > + */ > > + if (fdir_info->txq_available_buf_count <=3D 0) { > > + uint16_t tmp_tail; > > + volatile struct i40e_tx_desc *tmp_txdp; > > + > > + tmp_tail =3D txq->tx_tail; > > + tmp_txdp =3D &txq->tx_ring[tmp_tail + 1]; > > + > > + do { > > + if ((tmp_txdp->cmd_type_offset_bsz & > > + > > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) =3D=3D > > + > > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) > > + fdir_info->txq_available_buf_count++; > > + else > > + break; > > + > > + tmp_tail +=3D 2; > > + if (tmp_tail >=3D txq->nb_tx_desc) > > + tmp_tail =3D 0; > > + } while (tmp_tail !=3D txq->tx_tail); > > + } > > + > > + /* > > + * if txq_available_buf_count > 0, just use the next one is ok, > > + * else wait for the next DD until it's set to make sure the data > > + * had been fetched by hardware > > + */ > > + if (fdir_info->txq_available_buf_count > 0) { > > + fdir_info->txq_available_buf_count--; > > + } else { > > + /* wait until the tx descriptor is ready */ > > + for (i =3D 0; i < I40E_FDIR_MAX_WAIT_US; i++) { > > + if ((txdp->cmd_type_offset_bsz & > > + > > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) =3D=3D > > + > > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) > > + break; > > + rte_delay_us(1); > > + } > > + if (i >=3D I40E_FDIR_MAX_WAIT_US) { > > + PMD_DRV_LOG(ERR, > > + "Failed to program FDIR filter: time out to get DD on > tx > > queue."); > > + return NULL; > > + } > > + } > Why wait for I40E_FDIR_MAX_WAIT_US but not return NULL immediately? Done > [...] >=20 >=20 > > i40e_flow_fdir_filter_programming(struct i40e_pf *pf, > > enum i40e_filter_pctype pctype, > > const struct i40e_fdir_filter_conf *filter, > > - bool add) > > + bool add, bool wait_status) > > { > > struct i40e_tx_queue *txq =3D pf->fdir.txq; > > struct i40e_rx_queue *rxq =3D pf->fdir.rxq; @@ -2011,8 +2092,10 @@ > > i40e_flow_fdir_filter_programming(struct i40e_pf *pf, > > volatile struct i40e_tx_desc *txdp; > > volatile struct i40e_filter_program_desc *fdirdp; > > uint32_t td_cmd; > > - uint16_t vsi_id, i; > > + uint16_t vsi_id; > > uint8_t dest; > > + uint32_t i; > > + uint8_t retry_count =3D 0; > > > > PMD_DRV_LOG(INFO, "filling filter programming descriptor."); > > fdirdp =3D (volatile struct i40e_filter_program_desc *) @@ -2087,7 > > +2170,8 @@ i40e_flow_fdir_filter_programming(struct i40e_pf *pf, > > > > PMD_DRV_LOG(INFO, "filling transmit descriptor."); > > txdp =3D &txq->tx_ring[txq->tx_tail + 1]; > > - txdp->buffer_addr =3D rte_cpu_to_le_64(pf->fdir.dma_addr); > > + txdp->buffer_addr =3D rte_cpu_to_le_64(pf->fdir.dma_addr[txq->tx_tail > > +/ 2]); > > + > [txq->tx_tail / 2] is not readable, how about use the avail pkt you get d= irectly? > Or another index to identify it? Have replaced with >> 1 > > td_cmd =3D I40E_TX_DESC_CMD_EOP | > > I40E_TX_DESC_CMD_RS | > > I40E_TX_DESC_CMD_DUMMY; > > @@ -2100,25 +2184,34 @@ i40e_flow_fdir_filter_programming(struct > i40e_pf *pf, > > txq->tx_tail =3D 0; > > /* Update the tx tail register */ > > rte_wmb(); > > + > > + /* capture the previous error report(if any) from rx ring */ > > + while ((i40e_check_fdir_programming_status(rxq) < 0) && > > + (++retry_count < 100)) > > + PMD_DRV_LOG(INFO, "previous error report captured."); > > + > Why check FDIR ring for 100 times? And "&&" is used here, the log is only= print if > the 100th check fails? No, it will print 100 times. The purpose of this code is to clean up the fdir rx queue. Have new an independent function for this > > > > -- > > 2.17.1