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Tue, 14 Dec 2021 14:51:25 +0000 From: "McDaniel, Timothy" To: "Shetty, Rashmi" , "dev@dpdk.org" CC: "jerinj@marvell.com" , "Van Haaren, Harry" , "Pathak, Pravin" , "Chen, Mike Ximing" Subject: RE: [PATCH] doc/dlb2: update dlb2 documentation Thread-Topic: [PATCH] doc/dlb2: update dlb2 documentation Thread-Index: AQHX6r97VFl4toLLzEqlOUeOcyllC6wyHmZg Date: Tue, 14 Dec 2021 14:51:25 +0000 Message-ID: References: <20211206163639.2220123-1-rashmi.shetty@intel.com> In-Reply-To: <20211206163639.2220123-1-rashmi.shetty@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.200.16 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ec3e92da-74b0-4555-5f64-08d9bf1133ee x-ms-traffictypediagnostic: SA2PR11MB5177:EE_ x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB3103.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ec3e92da-74b0-4555-5f64-08d9bf1133ee X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Dec 2021 14:51:25.4596 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LUEU7WEXFi8pqrU0tGyUg9cnMecasKJ7KH+YWRfBKHMfYB8NC01plX8kkYCZQUz2aCFZHnOxj1xAuK1PwS/O/2DXLk3/MSwRbFubPgDrtNo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR11MB5177 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Shetty, Rashmi > Sent: Monday, December 6, 2021 10:37 AM > To: dev@dpdk.org > Cc: jerinj@marvell.com; Van Haaren, Harry ; > Pathak, Pravin ; Chen, Mike Ximing > ; McDaniel, Timothy > ; Shetty, Rashmi > Subject: [PATCH] doc/dlb2: update dlb2 documentation >=20 > Number of direct credits, atomic inflight and history list sizes > are updated to what is supported in DLB2.0. Revised Class of Service > section is added. >=20 > Signed-off-by: Rashmi Shetty > --- > doc/guides/eventdevs/dlb2.rst | 32 +++++++++++--------------------- > 1 file changed, 11 insertions(+), 21 deletions(-) >=20 > diff --git a/doc/guides/eventdevs/dlb2.rst b/doc/guides/eventdevs/dlb2.rs= t > index bce984ca08..c2887a71dc 100644 > --- a/doc/guides/eventdevs/dlb2.rst > +++ b/doc/guides/eventdevs/dlb2.rst > @@ -151,7 +151,7 @@ load-balanced queues, and directed credits are used f= or > directed queues. > These pools' sizes are controlled by the nb_events_limit field in struct > rte_event_dev_config. The load-balanced pool is sized to contain > nb_events_limit credits, and the directed pool is sized to contain > -nb_events_limit/4 credits. The directed pool size can be overridden with= the > +nb_events_limit/2 credits. The directed pool size can be overridden with= the > num_dir_credits devargs argument, like so: >=20 > .. code-block:: console > @@ -239,8 +239,8 @@ queue A. > Due to this, workers should stop retrying after a time, release the even= ts it > is attempting to enqueue, and dequeue more events. It is important that = the > worker release the events and don't simply set them aside to retry the e= nqueue > -again later, because the port has limited history list size (by default,= twice > -the port's dequeue_depth). > +again later, because the port has limited history list size (by default,= same > +as port's dequeue_depth). >=20 > Priority > ~~~~~~~~ > @@ -309,17 +309,11 @@ scheduled. The likelihood of this case depends on t= he > eventdev configuration, > traffic behavior, event processing latency, potential for a worker to be > interrupted or otherwise delayed, etc. >=20 > -By default, the PMD allocates 16 buffer entries for each load-balanced q= ueue, > -which provides an even division across all 128 queues but potentially wa= stes > +By default, the PMD allocates 64 buffer entries for each load-balanced q= ueue, > +which provides an even division across all 32 queues but potentially was= tes > buffer space (e.g. if not all queues are used, or aren't used for atomic > scheduling). >=20 > -The PMD provides a dev arg to override the default per-queue allocation.= To > -increase per-queue atomic-inflight allocation to (for example) 64: > - > - .. code-block:: console > - > - --allow ea:00.0,atm_inflights=3D64 >=20 > QID Depth Threshold > ~~~~~~~~~~~~~~~~~~~ > @@ -337,7 +331,7 @@ Per queue threshold metrics are tracked in the DLB > xstats, and are also > returned in the impl_opaque field of each received event. >=20 > The per qid threshold can be specified as part of the device args, and > -can be applied to all queue, a range of queues, or a single queue, as > +can be applied to all queues, a range of queues, or a single queue, as > shown below. >=20 > .. code-block:: console > @@ -350,14 +344,10 @@ Class of service > ~~~~~~~~~~~~~~~~ >=20 > DLB supports provisioning the DLB bandwidth into 4 classes of service. > +By default, each of the 4 classes (0-3) correspond to 25% of the DLB > +hardware bandwidth. >=20 > -- Class 4 corresponds to 40% of the DLB hardware bandwidth > -- Class 3 corresponds to 30% of the DLB hardware bandwidth > -- Class 2 corresponds to 20% of the DLB hardware bandwidth > -- Class 1 corresponds to 10% of the DLB hardware bandwidth > -- Class 0 corresponds to don't care > - > -The classes are applied globally to the set of ports contained in this > +The classes are applied globally to the set of ports contained in the > scheduling domain, which is more appropriate for the bifurcated > PMD than for the PF PMD, since the PF PMD supports just 1 scheduling > domain. > @@ -366,7 +356,7 @@ Class of service can be specified in the devargs, as > follows >=20 > .. code-block:: console >=20 > - --allow ea:00.0,cos=3D<0..4> > + --allow ea:00.0,cos=3D<0..3> >=20 > Use X86 Vector Instructions > ~~~~~~~~~~~~~~~~~~~~~~~~~~~ > @@ -379,4 +369,4 @@ follows >=20 > .. code-block:: console >=20 > - --allow ea:00.0,vector_opts_enabled=3D > + --allow ea:00.0,vector_opts_enable=3D > -- > 2.25.1 Reviewed-by: Timothy McDaniel