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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Kai Ji > ________________________________ From: Power, Ciara Sent: 27 October 2023 15:23 To: dev@dpdk.org Cc: Power, Ciara ; Dooley, Brian ; stable@dpdk.org ; Ji, Kai Subject: [PATCH] crypto/qat: fix build when no openssl exists Previously some compilation errors existed when no openssl was installed on the system, and intel-ipsec-mb was installed, due to missing headers and macros. This patch fixes the issue by adding in extra ifdefs around openssl specific code paths, and by adding the relevant macros explicitly in QAT code so it does not depend on openssl at all. Fixes: ca0ba0e48129 ("crypto/qat: default to IPsec MB for computations") Cc: brian.dooley@intel.com Cc: stable@dpdk.org Signed-off-by: Ciara Power --- drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 2 ++ drivers/crypto/qat/qat_sym.c | 2 ++ drivers/crypto/qat/qat_sym.h | 6 ++++-- drivers/crypto/qat/qat_sym_session.c | 13 ++++++------- drivers/crypto/qat/qat_sym_session.h | 3 +++ 5 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/= qat/dev/qat_crypto_pmd_gens.h index 37647374d5..eebf2e6eb8 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h @@ -24,6 +24,7 @@ (ICP_QAT_FW_COMN_STATUS_FLAG_OK =3D=3D \ ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(resp->comn_hdr.comn_status)) +#ifdef RTE_QAT_OPENSSL static __rte_always_inline int op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst, uint8_t *iv, int ivlen, int srclen, @@ -48,6 +49,7 @@ op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst, QAT_DP_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed"); return -EINVAL; } +#endif static __rte_always_inline uint32_t qat_bpicipher_preprocess(struct qat_sym_session *ctx, diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 936c2615e4..6e03bde841 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -2,7 +2,9 @@ * Copyright(c) 2015-2023 Intel Corporation */ +#ifdef RTE_QAT_OPENSSL #include +#endif #include #include diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index d19cadde86..b4e19e3015 100644 --- a/drivers/crypto/qat/qat_sym.h +++ b/drivers/crypto/qat/qat_sym.h @@ -9,7 +9,9 @@ #include #ifdef BUILD_QAT_SYM +#ifdef RTE_QAT_OPENSSL #include +#endif #include #include "qat_common.h" @@ -133,6 +135,7 @@ uint16_t qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops); +#ifdef RTE_QAT_OPENSSL /** Encrypt a single partial block * Depends on openssl libcrypto * Uses ECB+XOR to do CFB encryption, same result, more performant @@ -161,8 +164,7 @@ bpi_cipher_encrypt(uint8_t *src, uint8_t *dst, QAT_DP_LOG(ERR, "libcrypto ECB cipher encrypt failed"); return -EINVAL; } - -#ifndef RTE_QAT_OPENSSL +#else static __rte_always_inline void bpi_cipher_ipsec(uint8_t *src, uint8_t *dst, uint8_t *iv, int srclen, uint64_t *expkey, IMB_MGR *m, uint8_t docsis_key_len) diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_= sym_session.c index 7831a677d0..9f4f6c3d93 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -4,10 +4,12 @@ #define OPENSSL_API_COMPAT 0x10100000L +#ifdef RTE_QAT_OPENSSL #include /* Needed to calculate pre-compute values = */ #include /* Needed to calculate pre-compute values = */ #include /* Needed to calculate pre-compute values = */ #include /* Needed for bpi runt block processing */ +#endif #ifndef RTE_QAT_OPENSSL #ifndef RTE_ARCH_ARM @@ -1272,24 +1274,21 @@ static int qat_hash_get_block_size(enum icp_qat_hw_= auth_algo qat_hash_alg) { switch (qat_hash_alg) { case ICP_QAT_HW_AUTH_ALGO_SHA1: - return SHA_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA224: - return SHA256_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA256: - return SHA256_CBLOCK; + return QAT_SHA_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA384: - return SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SHA512: - return SHA512_CBLOCK; + return QAT_SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_GALOIS_128: return 16; case ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC: return ICP_QAT_HW_AES_BLK_SZ; case ICP_QAT_HW_AUTH_ALGO_MD5: - return MD5_CBLOCK; + return QAT_MD5_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_DELIMITER: /* return maximum block size in this case */ - return SHA512_CBLOCK; + return QAT_SHA512_CBLOCK; case ICP_QAT_HW_AUTH_ALGO_SM3: return QAT_SM3_BLOCK_SIZE; default: diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_= sym_session.h index 674a62ee12..9209e2e8df 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -69,6 +69,9 @@ (!!((flags) & (flag))) #define QAT_SM3_BLOCK_SIZE 64 +#define QAT_SHA_CBLOCK 64 +#define QAT_SHA512_CBLOCK 128 +#define QAT_MD5_CBLOCK 64 enum qat_sym_proto_flag { QAT_CRYPTO_PROTO_FLAG_NONE =3D 0, -- 2.25.1 --_000_SN6PR11MB340832D485B0859291E3D6F781DCASN6PR11MB3408namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Acked-by: Kai Ji <kai.ji@intel.com&g= t;
From: Power, Ciara <ciar= a.power@intel.com>
Sent: 27 October 2023 15:23
To: dev@dpdk.org <dev@dpdk.org>
Cc: Power, Ciara <ciara.power@intel.com>; Dooley, Brian <br= ian.dooley@intel.com>; stable@dpdk.org <stable@dpdk.org>; Ji, Kai = <kai.ji@intel.com>
Subject: [PATCH] crypto/qat: fix build when no openssl exists
 
Previously some compilation errors existed when no= openssl
was installed on the system, and intel-ipsec-mb was installed,
due to missing headers and macros.

This patch fixes the issue by adding in extra ifdefs around openssl
specific code paths, and by adding the relevant macros explicitly
in QAT code so it does not depend on openssl at all.

Fixes: ca0ba0e48129 ("crypto/qat: default to IPsec MB for computations= ")
Cc: brian.dooley@intel.com
Cc: stable@dpdk.org

Signed-off-by: Ciara Power <ciara.power@intel.com>
---
 drivers/crypto/qat/dev/qat_crypto_pmd_gens.h |  2 ++
 drivers/crypto/qat/qat_sym.c       = ;          |  2 ++
 drivers/crypto/qat/qat_sym.h       = ;          |  6 ++++--  drivers/crypto/qat/qat_sym_session.c     &nb= sp;   | 13 ++++++-------
 drivers/crypto/qat/qat_sym_session.h     &nb= sp;   |  3 +++
 5 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/= qat/dev/qat_crypto_pmd_gens.h
index 37647374d5..eebf2e6eb8 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
@@ -24,6 +24,7 @@
         (ICP_QAT_FW_COMN_STATUS_FL= AG_OK =3D=3D \
         ICP_QAT_FW_COMN_RESP_CRYPT= O_STAT_GET(resp->comn_hdr.comn_status))
 
+#ifdef RTE_QAT_OPENSSL
 static __rte_always_inline int
 op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
            &nb= sp;    uint8_t *iv, int ivlen, int srclen,
@@ -48,6 +49,7 @@ op_bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
         QAT_DP_LOG(ERR, "libc= rypto ECB cipher decrypt for BPI IV failed");
         return -EINVAL;
 }
+#endif
 
 static __rte_always_inline uint32_t
 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 936c2615e4..6e03bde841 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -2,7 +2,9 @@
  * Copyright(c) 2015-2023 Intel Corporation
  */
 
+#ifdef RTE_QAT_OPENSSL
 #include <openssl/evp.h>
+#endif
 
 #include <rte_mempool.h>
 #include <rte_mbuf.h>
diff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h index d19cadde86..b4e19e3015 100644
--- a/drivers/crypto/qat/qat_sym.h
+++ b/drivers/crypto/qat/qat_sym.h
@@ -9,7 +9,9 @@
 #include <rte_net_crc.h>
 
 #ifdef BUILD_QAT_SYM
+#ifdef RTE_QAT_OPENSSL
 #include <openssl/evp.h>
+#endif
 #include <rte_security_driver.h>
 
 #include "qat_common.h"
@@ -133,6 +135,7 @@ uint16_t
 qat_sym_dequeue_burst(void *qp, struct rte_crypto_op **ops,
            &nb= sp;    uint16_t nb_ops);
 
+#ifdef RTE_QAT_OPENSSL
 /** Encrypt a single partial block
  *  Depends on openssl libcrypto
  *  Uses ECB+XOR to do CFB encryption, same result, more perform= ant
@@ -161,8 +164,7 @@ bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
         QAT_DP_LOG(ERR, "libc= rypto ECB cipher encrypt failed");
         return -EINVAL;
 }
-
-#ifndef RTE_QAT_OPENSSL
+#else
 static __rte_always_inline void
 bpi_cipher_ipsec(uint8_t *src, uint8_t *dst, uint8_t *iv, int srclen,=
            &nb= sp;    uint64_t *expkey, IMB_MGR *m, uint8_t docsis_key_len)=
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_= sym_session.c
index 7831a677d0..9f4f6c3d93 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -4,10 +4,12 @@
 
 #define OPENSSL_API_COMPAT 0x10100000L
 
+#ifdef RTE_QAT_OPENSSL
 #include <openssl/sha.h>      &nb= sp; /* Needed to calculate pre-compute values */
 #include <openssl/aes.h>      &nb= sp; /* Needed to calculate pre-compute values */
 #include <openssl/md5.h>      &nb= sp; /* Needed to calculate pre-compute values */
 #include <openssl/evp.h>      &nb= sp; /* Needed for bpi runt block processing */
+#endif
 
 #ifndef RTE_QAT_OPENSSL
 #ifndef RTE_ARCH_ARM
@@ -1272,24 +1274,21 @@ static int qat_hash_get_block_size(enum icp_qat_hw_= auth_algo qat_hash_alg)
 {
         switch (qat_hash_alg) {          case ICP_QAT_HW_AUTH_ALGO_= SHA1:
-            &n= bsp;  return SHA_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= SHA224:
-            &n= bsp;  return SHA256_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= SHA256:
-            &n= bsp;  return SHA256_CBLOCK;
+            &n= bsp;  return QAT_SHA_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= SHA384:
-            &n= bsp;  return SHA512_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= SHA512:
-            &n= bsp;  return SHA512_CBLOCK;
+            &n= bsp;  return QAT_SHA512_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= GALOIS_128:
            &nb= sp;    return 16;
         case ICP_QAT_HW_AUTH_ALGO_= AES_XCBC_MAC:
            &nb= sp;    return ICP_QAT_HW_AES_BLK_SZ;
         case ICP_QAT_HW_AUTH_ALGO_= MD5:
-            &n= bsp;  return MD5_CBLOCK;
+            &n= bsp;  return QAT_MD5_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= DELIMITER:
            &nb= sp;    /* return maximum block size in this case */
-            &n= bsp;  return SHA512_CBLOCK;
+            &n= bsp;  return QAT_SHA512_CBLOCK;
         case ICP_QAT_HW_AUTH_ALGO_= SM3:
            &nb= sp;    return QAT_SM3_BLOCK_SIZE;
         default:
diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_= sym_session.h
index 674a62ee12..9209e2e8df 100644
--- a/drivers/crypto/qat/qat_sym_session.h
+++ b/drivers/crypto/qat/qat_sym_session.h
@@ -69,6 +69,9 @@
         (!!((flags) & (flag)))=
 
 #define QAT_SM3_BLOCK_SIZE      64
+#define QAT_SHA_CBLOCK 64
+#define QAT_SHA512_CBLOCK 128
+#define QAT_MD5_CBLOCK 64
 
 enum qat_sym_proto_flag {
         QAT_CRYPTO_PROTO_FLAG_NONE= =3D 0,
--
2.25.1

--_000_SN6PR11MB340832D485B0859291E3D6F781DCASN6PR11MB3408namp_--