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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB3504.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c39c5d67-f349-486f-836f-08da348c5d2b X-MS-Exchange-CrossTenant-originalarrivaltime: 13 May 2022 02:57:48.9232 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: c5ZOoiGQovDrNFqQl2RdWBxkm9bRM0z/7tWoSAwAlKNrVH60kvq8XLFxfwr+f/t4hzZRi16BQjy5yuuLOb2rMQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR11MB4243 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Pei, Andy > Sent: Wednesday, April 27, 2022 4:30 PM > To: dev@dpdk.org > Cc: Xia, Chenbo ; maxime.coquelin@redhat.com; Cao, > Gang ; Liu, Changpeng > Subject: [PATCH v7 16/18] vdpa/ifc/base: access correct register for blk > device >=20 > 1.last_avail_idx is lower 16 bit of the register. > 2.address of ring_state register is different between net and blk device. Not a good commit log. The commit log should illustrate more on what's the commit is doing. Thanks, Chenbo >=20 > Signed-off-by: Andy Pei > --- > drivers/vdpa/ifc/base/ifcvf.c | 36 +++++++++++++++++++++++++++++------- > drivers/vdpa/ifc/base/ifcvf.h | 1 + > 2 files changed, 30 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.= c > index d10c1fd..4d5881a 100644 > --- a/drivers/vdpa/ifc/base/ifcvf.c > +++ b/drivers/vdpa/ifc/base/ifcvf.c > @@ -218,10 +218,18 @@ > &cfg->queue_used_hi); > IFCVF_WRITE_REG16(hw->vring[i].size, &cfg->queue_size); >=20 > - *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4) =3D > - (u32)hw->vring[i].last_avail_idx | > - ((u32)hw->vring[i].last_used_idx << 16); > + if (hw->is_blk =3D=3D IFCVF_BLK) { > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > + i * IFCVF_LM_CFG_SIZE) =3D > + (u32)hw->vring[i].last_avail_idx | > + ((u32)hw->vring[i].last_used_idx << 16); > + } else if (hw->is_blk =3D=3D IFCVF_NET) { > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > + (i / 2) * IFCVF_LM_CFG_SIZE + > + (i % 2) * 4) =3D > + (u32)hw->vring[i].last_avail_idx | > + ((u32)hw->vring[i].last_used_idx << 16); > + } >=20 > IFCVF_WRITE_REG16(i + 1, &cfg->queue_msix_vector); > if (IFCVF_READ_REG16(&cfg->queue_msix_vector) =3D=3D > @@ -254,9 +262,23 @@ > IFCVF_WRITE_REG16(i, &cfg->queue_select); > IFCVF_WRITE_REG16(0, &cfg->queue_enable); > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg- > >queue_msix_vector); > - ring_state =3D *(u32 *)(hw->lm_cfg + IFCVF_LM_RING_STATE_OFFSET > + > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4); > - hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > + > + if (hw->is_blk) { > + ring_state =3D *(u32 *)(hw->lm_cfg + > + IFCVF_LM_RING_STATE_OFFSET + > + i * IFCVF_LM_CFG_SIZE); > + } else if (hw->is_blk =3D=3D IFCVF_NET) { > + ring_state =3D *(u32 *)(hw->lm_cfg + > + IFCVF_LM_RING_STATE_OFFSET + > + (i / 2) * IFCVF_LM_CFG_SIZE + > + (i % 2) * 4); > + } > + > + if (hw->is_blk =3D=3D IFCVF_BLK) > + hw->vring[i].last_avail_idx =3D > + (u16)(ring_state & IFCVF_16_BIT_MASK); > + else if (hw->is_blk =3D=3D IFCVF_NET) > + hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > hw->vring[i].last_used_idx =3D (u16)(ring_state >> 16); > } > } > diff --git a/drivers/vdpa/ifc/base/ifcvf.h b/drivers/vdpa/ifc/base/ifcvf.= h > index 8591ef1..ff11b12 100644 > --- a/drivers/vdpa/ifc/base/ifcvf.h > +++ b/drivers/vdpa/ifc/base/ifcvf.h > @@ -65,6 +65,7 @@ > #define IFCVF_MEDIATED_VRING 0x200000000000 >=20 > #define IFCVF_32_BIT_MASK 0xffffffff > +#define IFCVF_16_BIT_MASK 0xffff >=20 > #ifndef VHOST_USER_PROTOCOL_F_CONFIG > #define VHOST_USER_PROTOCOL_F_CONFIG 9 > -- > 1.8.3.1