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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR11MB3504.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f0fc1d4a-64ce-4613-7e05-08da3c91a864 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 May 2022 07:55:51.9116 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ohP0+iNkn8HR1XgC9fcaZ6NArCZoBye3XMe6JvgagLFDtst3/RCmbIFJLXM2y3v6pvtP9SYjIYlaLJEib32wKg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5596 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Pei, Andy > Sent: Wednesday, May 18, 2022 8:14 PM > To: dev@dpdk.org > Cc: Xia, Chenbo ; maxime.coquelin@redhat.com; Cao, > Gang ; Liu, Changpeng ; Xu, > Rosen ; Xiao, QimaiX > Subject: [PATCH v8 13/13] vdpa/ifc/base: access correct register for blk > device >=20 > Register address is different between net and blk device. > We are re-use most of the code, when register address is Re-using With this fixed: Reviewed-by: Chenbo Xia > different, we have to check net and blk device go through > different code. >=20 > Signed-off-by: Andy Pei > --- > drivers/vdpa/ifc/base/ifcvf.c | 34 +++++++++++++++++++++++++++------- > 1 file changed, 27 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/vdpa/ifc/base/ifcvf.c b/drivers/vdpa/ifc/base/ifcvf.= c > index d10c1fd..dd475a7 100644 > --- a/drivers/vdpa/ifc/base/ifcvf.c > +++ b/drivers/vdpa/ifc/base/ifcvf.c > @@ -218,10 +218,17 @@ > &cfg->queue_used_hi); > IFCVF_WRITE_REG16(hw->vring[i].size, &cfg->queue_size); >=20 > - *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4) =3D > - (u32)hw->vring[i].last_avail_idx | > - ((u32)hw->vring[i].last_used_idx << 16); > + if (hw->device_type =3D=3D IFCVF_BLK) > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > + i * IFCVF_LM_CFG_SIZE) =3D > + (u32)hw->vring[i].last_avail_idx | > + ((u32)hw->vring[i].last_used_idx << 16); > + else > + *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET + > + (i / 2) * IFCVF_LM_CFG_SIZE + > + (i % 2) * 4) =3D > + (u32)hw->vring[i].last_avail_idx | > + ((u32)hw->vring[i].last_used_idx << 16); >=20 > IFCVF_WRITE_REG16(i + 1, &cfg->queue_msix_vector); > if (IFCVF_READ_REG16(&cfg->queue_msix_vector) =3D=3D > @@ -254,9 +261,22 @@ > IFCVF_WRITE_REG16(i, &cfg->queue_select); > IFCVF_WRITE_REG16(0, &cfg->queue_enable); > IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg- > >queue_msix_vector); > - ring_state =3D *(u32 *)(hw->lm_cfg + IFCVF_LM_RING_STATE_OFFSET > + > - (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4); > - hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > + > + if (hw->device_type =3D=3D IFCVF_BLK) > + ring_state =3D *(u32 *)(hw->lm_cfg + > + IFCVF_LM_RING_STATE_OFFSET + > + i * IFCVF_LM_CFG_SIZE); > + else > + ring_state =3D *(u32 *)(hw->lm_cfg + > + IFCVF_LM_RING_STATE_OFFSET + > + (i / 2) * IFCVF_LM_CFG_SIZE + > + (i % 2) * 4); > + > + if (hw->device_type =3D=3D IFCVF_BLK) > + hw->vring[i].last_avail_idx =3D > + (u16)(ring_state & IFCVF_16_BIT_MASK); > + else > + hw->vring[i].last_avail_idx =3D (u16)(ring_state >> 16); > hw->vring[i].last_used_idx =3D (u16)(ring_state >> 16); > } > } > -- > 1.8.3.1