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To: "Tan, Jianfeng" , Ferruh Yigit , Thomas Monjalon CC: "dev@dpdk.org" , "stable@dpdk.org" , Jingjing Wu , Shijith Thotton , Gregory Etelson , Harish Patil , George Prekas , Sergio Gonzalez Monroy , Rasesh Mody Thread-Topic: [dpdk-dev] [PATCH v2] igb_uio: add config option to control reset Thread-Index: AQHTVE+D/91aOMvv1U6frovcDksqeqMDCTFw Date: Fri, 3 Nov 2017 19:42:45 +0000 Message-ID: References: <20171103003005.44339-1-ferruh.yigit@intel.com> <20171103005100.44633-1-ferruh.yigit@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=lee.roberts@hpe.com; x-originating-ip: [15.203.227.13] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; TU4PR8401MB0687; 6:fgpj1Ra9T5btSXaCM6hS/gI/6OLz16M1rmCa5FKvQOY9QHGOpL3al6nvpiNw/EiQPeSCwhbE6+79jBaMj+H4Dx2yTLg3IHUJYhUOSiVxoT0z4lVi3uBLk4uPCGgd2tDfa4oSuLV9FQZhSmEqQ4m9lvDf2O/szbJB6Yq3+x5cAhSPWDnp1v+16cFXWIVJN1D+2OJ0eMU/et3KKAHXlC2x8Obs9fvbpveHRQ8kr1lw9+gn7fZmONRGq9wM4LOJpb/trbYkQGtaKaYV0Cd/C5gvbyCvz++kCrm37l+XnhdTsWgI9xUkO1qCYWZBlGSS7UIK1d8rplYZVZKXkL663GY0cs81EQQ5otgJUGDePqVTz9s=; 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DIR:OUT; SFP:1102; SCL:1; SRVR:TU4PR8401MB0687; H:TU4PR8401MB0687.NAMPRD84.PROD.OUTLOOK.COM; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: hpe.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d3ac67ad-b222-4be9-2206-08d522f30e9f X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2017 19:42:45.9406 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-Transport-CrossTenantHeadersStamped: TU4PR8401MB0687 X-OriginatorOrg: hpe.com Subject: Re: [dpdk-dev] [PATCH v2] igb_uio: add config option to control reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Nov 2017 19:42:49 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Tan, Jianfeng > Sent: Thursday, November 02, 2017 8:57 PM > To: Ferruh Yigit ; Thomas Monjalon > Cc: dev@dpdk.org; stable@dpdk.org; Jingjing Wu ; S= hijith Thotton > ; Gregory Etelson ; = Harish Patil > ; George Prekas ; Sergio = Gonzalez Monroy > ; Rasesh Mody > Subject: Re: [dpdk-dev] [PATCH v2] igb_uio: add config option to control = reset >=20 >=20 >=20 > On 11/3/2017 8:51 AM, Ferruh Yigit wrote: > > Adding a compile time configuration option to control device reset done > > during DPDK application exit. > > > > Config option is CONFIG_RTE_EAL_IGB_UIO_RESET and enabled by default, > > so by default reset will happen. Having this reset is safer to be sure > > device left in a proper case. > > > > But for special cases [1] it is possible to disable the config option > > to prevent the device reset. > > > > [1] > > http://dpdk.org/ml/archives/dev/2017-November/080927.html > > > > Fixes: b58eedfc7dd5 ("igb_uio: issue FLR during open and release of dev= ice file") > > Cc: stable@dpdk.org > > > > Signed-off-by: Ferruh Yigit >=20 > Realize that we do have a pci_clear_master() in the release() to disable > the DMA from device until the next open() will enable the DMA again . > Here is my: >=20 > Reviewed-by: Jianfeng Tan >=20 > Thanks, > Jianfeng >=20 > > --- > > Cc: Jianfeng Tan > > Cc: Jingjing Wu > > Cc: Shijith Thotton > > Cc: Gregory Etelson > > Cc: Harish Patil > > Cc: George Prekas > > Cc: Sergio Gonzalez Monroy > > Cc: Rasesh Mody > > > > v2: > > * fix typo in commit log > > --- > > config/common_base | 1 + > > config/common_linuxapp | 1 + > > lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 2 ++ > > 3 files changed, 4 insertions(+) > > > > diff --git a/config/common_base b/config/common_base > > index 82ee75456..2a9947420 100644 > > --- a/config/common_base > > +++ b/config/common_base > > @@ -102,6 +102,7 @@ CONFIG_RTE_LIBEAL_USE_HPET=3Dn > > CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=3Dn > > CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=3Dn > > CONFIG_RTE_EAL_IGB_UIO=3Dn > > +CONFIG_RTE_EAL_IGB_UIO_RESET=3Dn > > CONFIG_RTE_EAL_VFIO=3Dn > > CONFIG_RTE_MALLOC_DEBUG=3Dn > > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dn > > diff --git a/config/common_linuxapp b/config/common_linuxapp > > index 74c7d64ec..b3a602909 100644 > > --- a/config/common_linuxapp > > +++ b/config/common_linuxapp > > @@ -37,6 +37,7 @@ CONFIG_RTE_EXEC_ENV_LINUXAPP=3Dy > > > > CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=3Dy > > CONFIG_RTE_EAL_IGB_UIO=3Dy > > +CONFIG_RTE_EAL_IGB_UIO_RESET=3Dy > > CONFIG_RTE_EAL_VFIO=3Dy > > CONFIG_RTE_KNI_KMOD=3Dy > > CONFIG_RTE_LIBRTE_KNI=3Dy > > diff --git a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c b/lib/librte_eal= /linuxapp/igb_uio/igb_uio.c > > index fd320d87d..0325722c0 100644 > > --- a/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > > +++ b/lib/librte_eal/linuxapp/igb_uio/igb_uio.c > > @@ -360,7 +360,9 @@ igbuio_pci_release(struct uio_info *info, struct in= ode *inode) > > /* stop the device from further DMA */ > > pci_clear_master(dev); > > > > +#ifdef RTE_EAL_IGB_UIO_RESET > > pci_reset_function(dev); > > +#endif > > > > return 0; > > } A compile time configuration option makes life very difficult for applicati= on providers. Consider the case where an application such as Open vSwitch with DPDK suppo= rt is being provided with a Linux distribution. One would want the Open vSwitch binary to suppo= rt as many vendor NICs as possible---without the need to recompile. With a change such as this, o= ne would need to have different versions of the kernel igb_uio module to support different NICs. The Linux kernel is already aware of, and provides work-arounds for, variou= s PCI quirks. For example, see linux/drivers/pci/quirks.c (http://elixir.free-electrons.c= om/linux/latest/source/drivers/pci/quirks.c). At this point in igb_uio.c, one is aware of the struct pci_dev "dev" for th= e device in question. Access to the vendor and device information should be simple: struct pci_dev { struct list_head bus_list; /* node in per-bus list */ struct pci_bus *bus; /* bus this device is on */ struct pci_bus *subordinate; /* bus this device bridges to */ void *sysdata; /* hook for sys-specific extension */ struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ struct pci_slot *slot; /* Physical slot this device is in */ unsigned int devfn; /* encoded device & function index */ unsigned short vendor; unsigned short device; unsigned short subsystem_vendor; unsigned short subsystem_device; ... One could imagine using logic to implement corresponding PCI quirks that ca= n be evaluated at runtime. For example (in pseudocode), if not (vendor =3D "Cavium" and device =3D "bnx2x") then pci_reset_function(dev); There are other possible implementations. If there are enough quirks, one = might have action functions defined---and a table of function pointers associated with each P= MD to select the proper action. - Lee Roberts =20