[dpdk-dev] [PATCH 1/2] common/qat: get version of QAT firmware

[dpdk-dev] [PATCH 1/2] common/qat: get version of QAT firmware

[Adam Dybkowski]

This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 89 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 3 files changed, 94 insertions(+)

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 1265c2a13..be10fc9bd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -121,6 +121,8 @@ struct icp_qat_fw_comn_resp {
 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
 
 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
 	icp_qat_fw_comn_req_hdr_t.service_type
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 9958789f0..93685aeb0 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -19,6 +19,7 @@
 #include "qat_comp.h"
 #include "adf_transport_access_macros.h"
 
+#define QAT_CQ_MAX_DEQ_RETRIES 10
 
 #define ADF_MAX_DESC				4096
 #define ADF_MIN_DESC				128
@@ -695,6 +696,94 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 	return resp_counter;
 }
 
+/* This is almost same as dequeue_op_burst, without the atomic, without stats
+ * and without the op. Dequeues one response.
+ */
+static uint8_t
+qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
+{
+	uint8_t result = 0;
+	uint8_t retries = 0;
+	struct qat_queue *queue = &(qp->rx_q);
+	struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
+			((uint8_t *)queue->base_addr + queue->head);
+
+	while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
+			*(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
+		/* loop waiting for response until we reach the timeout */
+		rte_delay_ms(20);
+	}
+
+	if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
+		/* response received, check status flag */
+		if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
+				resp_msg->comn_hdr.comn_status) ==
+				ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+			/* success */
+			memcpy(out_data, resp_msg, queue->msg_size);
+			result = 1;
+		}
+
+		queue->head = adf_modulo(queue->head + queue->msg_size,
+				queue->modulo_mask);
+		rxq_free_desc(qp, queue);
+	}
+
+	return result;
+}
+
+/* Sends a NULL message and extracts QAT fw version from the response.
+ * Used to determine detailed capabilities based on the fw version number.
+ * This assumes that there are no inflight messages, i.e. assumes there's space
+ * on the qp, one message is sent and only one response collected.
+ * Returns fw version number or a negative error code.
+ */
+int
+qat_cq_get_fw_version(struct qat_qp *qp)
+{
+	struct qat_queue *queue = &(qp->tx_q);
+	uint8_t *base_addr = (uint8_t *)queue->base_addr;
+	struct icp_qat_fw_comn_req null_msg;
+	struct icp_qat_fw_comn_resp response;
+
+	/* prepare the NULL request */
+	memset(&null_msg, 0, sizeof(null_msg));
+	null_msg.comn_hdr.hdr_flags =
+		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+	null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+	null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+	QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
+#endif
+
+	/* send the NULL request */
+	memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
+	queue->tail = adf_modulo(queue->tail + queue->msg_size,
+			queue->modulo_mask);
+	txq_write_tail(qp, queue);
+
+	/* receive a response */
+	memset(&response, 0, sizeof(response));
+	if (qat_cq_dequeue_response(qp, &response)) {
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+		QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
+				sizeof(response));
+#endif
+		/* if LW0 bit 24 is set - then the fw version was returned */
+		if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
+			return response.resrvd[0]; /* return LW4 */
+		else
+			return 0; /* not set - we don't know fw version */
+	}
+
+	QAT_LOG(ERR, "No response received");
+	return -EINVAL;
+}
+
 __rte_weak int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
 			  void *op_cookie __rte_unused,
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 0b95ea3c9..47ad5dd20 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,6 +103,9 @@ int
 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 			enum qat_service_type service);
 
+int
+qat_cq_get_fw_version(struct qat_qp *qp);
+
 /* Needed for weak function*/
 int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
-- 
2.17.1

[dpdk-dev] [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 doc/guides/cryptodevs/qat.rst          |  9 ++++-----
 doc/guides/rel_notes/release_20_05.rst |  7 +++++++
 drivers/crypto/qat/qat_sym_pmd.c       | 23 +++++++++++++++++++++++
 drivers/crypto/qat/qat_sym_pmd.h       |  5 +++++
 drivers/crypto/qat/qat_sym_session.c   | 17 +++++++++++------
 5 files changed, 50 insertions(+), 11 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 06985e319..2e0dc1b00 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:
    +------------------+-----------+-------------+----------+----------+
    | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
    +==================+===========+=============+==========+==========+
-   | NULL CIPHER      | Y         | 3           | 3        | Y        |
+   | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
-   | SNOW3G UEA2      | 3         | Y           | 3        | 3        |
+   | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | ZUC EEA3         | 3         | 3           | 2&3      | 3        |
+   | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | AES CTR          | Y         | 3           | 3        | Y        |
+   | AES CTR          | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
 
 * The combinations marked as "Y" are supported on all QAT hardware versions.
 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
-* The combinations marked as "3" are supported on GEN3 QAT hardware only.
 
 
 Limitations
diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 2190eaf85..bdfa64973 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -56,6 +56,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
+
+  Enabled handling of mixed algorithms in encrypted digest hash-cipher
+  (generation) and cipher-hash (verification) requests in QAT PMD
+  when running on GEN2 QAT hardware with particular firmware versions
+  (GEN3 support was added in DPDK 20.02).
+
 
 Removed Items
 -------------
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 666ede726..69b11ec78 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -14,6 +14,8 @@
 #include "qat_sym_session.h"
 #include "qat_sym_pmd.h"
 
+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
+
 uint8_t cryptodev_qat_driver_id;
 
 static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
@@ -187,6 +189,27 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 				qat_sgl_dst);
 	}
 
+	/* Get fw version from QAT (GEN2), skip if we've got it already */
+	if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities
+			& QAT_SYM_CAP_VALID)) {
+		ret = qat_cq_get_fw_version(qp);
+
+		if (ret < 0)
+			return ret;
+
+		if (ret != 0)
+			QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
+					(ret >> 24) & 0xff,
+					(ret >> 16) & 0xff,
+					(ret >> 8) & 0xff);
+
+		/* set capabilities based on the fw version */
+		qat_private->internal_capabilities = QAT_SYM_CAP_VALID |
+				((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
+						QAT_SYM_CAP_MIXED_CRYPTO : 0);
+		ret = 0;
+	}
+
 	return ret;
 }
 
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index a32c25abc..a5a31e512 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -15,6 +15,10 @@
 /** Intel(R) QAT Symmetric Crypto PMD driver name */
 #define CRYPTODEV_NAME_QAT_SYM_PMD	crypto_qat
 
+/* Internal capabilities */
+#define QAT_SYM_CAP_MIXED_CRYPTO	(1 << 0)
+#define QAT_SYM_CAP_VALID		(1 << 31)
+
 extern uint8_t cryptodev_qat_driver_id;
 
 /** private data structure for a QAT device.
@@ -29,6 +33,7 @@ struct qat_sym_dev_private {
 	const struct rte_cryptodev_capabilities *qat_dev_capabilities;
 	/* QAT device symmetric crypto capabilities */
 	uint16_t min_enq_burst_threshold;
+	uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
 };
 
 int
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 4359f2f0b..bf6af60aa 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,
 }
 
 static void
-qat_sym_session_handle_mixed(struct qat_sym_session *session)
+qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,
+		struct qat_sym_session *session)
 {
+	const struct qat_sym_dev_private *qat_private = dev->data->dev_private;
+	enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &
+			QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;
+
 	if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);
 	} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);
 	} else if ((session->aes_cmac ||
@@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 			session->qat_cipher_alg ==
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session, 0);
 	}
 }
@@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
@@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
-- 
2.17.1

Re: [dpdk-dev] [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Trahe, Fiona]

Hi Adam,

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Thursday, March 12, 2020 2:14 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT
> 
> This patch adds handling of mixed hash-cipher algorithms
> available on GEN2 QAT in particular firmware versions.
> Also the documentation is updated to show the mixed crypto
> algorithms are supported on QAT GEN2.
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> ---
>  doc/guides/cryptodevs/qat.rst          |  9 ++++-----
>  doc/guides/rel_notes/release_20_05.rst |  7 +++++++
>  drivers/crypto/qat/qat_sym_pmd.c       | 23 +++++++++++++++++++++++
>  drivers/crypto/qat/qat_sym_pmd.h       |  5 +++++
>  drivers/crypto/qat/qat_sym_session.c   | 17 +++++++++++------
>  5 files changed, 50 insertions(+), 11 deletions(-)
> 
> diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
> index 06985e319..2e0dc1b00 100644
> --- a/doc/guides/cryptodevs/qat.rst
> +++ b/doc/guides/cryptodevs/qat.rst
> @@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:
>     +------------------+-----------+-------------+----------+----------+
>     | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
>     +==================+===========+=============+==========+==========+
> -   | NULL CIPHER      | Y         | 3           | 3        | Y        |
> +   | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
>     +------------------+-----------+-------------+----------+----------+
> -   | SNOW3G UEA2      | 3         | Y           | 3        | 3        |
> +   | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
>     +------------------+-----------+-------------+----------+----------+
> -   | ZUC EEA3         | 3         | 3           | 2&3      | 3        |
> +   | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
>     +------------------+-----------+-------------+----------+----------+
> -   | AES CTR          | Y         | 3           | 3        | Y        |
> +   | AES CTR          | Y         | 2&3         | 2&3      | Y        |
>     +------------------+-----------+-------------+----------+----------+
> 
>  * The combinations marked as "Y" are supported on all QAT hardware versions.
>  * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
> -* The combinations marked as "3" are supported on GEN3 QAT hardware only.
> 
> 
>  Limitations
> diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
> index 2190eaf85..bdfa64973 100644
> --- a/doc/guides/rel_notes/release_20_05.rst
> +++ b/doc/guides/rel_notes/release_20_05.rst
> @@ -56,6 +56,13 @@ New Features
>       Also, make sure to start the actual text at the margin.
>       =========================================================
> 
> +* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
> +
> +  Enabled handling of mixed algorithms in encrypted digest hash-cipher
> +  (generation) and cipher-hash (verification) requests in QAT PMD
> +  when running on GEN2 QAT hardware with particular firmware versions
> +  (GEN3 support was added in DPDK 20.02).
> +
> 
>  Removed Items
>  -------------
> diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
> index 666ede726..69b11ec78 100644
> --- a/drivers/crypto/qat/qat_sym_pmd.c
> +++ b/drivers/crypto/qat/qat_sym_pmd.c
> @@ -14,6 +14,8 @@
>  #include "qat_sym_session.h"
>  #include "qat_sym_pmd.h"
> 
> +#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
> +
>  uint8_t cryptodev_qat_driver_id;
> 
>  static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
> @@ -187,6 +189,27 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
>  				qat_sgl_dst);
>  	}
> 
> +	/* Get fw version from QAT (GEN2), skip if we've got it already */
> +	if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities
> +			& QAT_SYM_CAP_VALID)) {
> +		ret = qat_cq_get_fw_version(qp);
> +
> +		if (ret < 0)
> +			return ret;
[Fiona] if this fails, then need to clean up the ring before returning

> +
> +		if (ret != 0)
> +			QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
> +					(ret >> 24) & 0xff,
> +					(ret >> 16) & 0xff,
> +					(ret >> 8) & 0xff);
[Fiona] add debug log with "unknown firmware version" in else case
> +
> +		/* set capabilities based on the fw version */
> +		qat_private->internal_capabilities = QAT_SYM_CAP_VALID |
> +				((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
> +						QAT_SYM_CAP_MIXED_CRYPTO : 0);
> +		ret = 0;
> +	}
> +
>  	return ret;
>  }
> 
> diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
> index a32c25abc..a5a31e512 100644
> --- a/drivers/crypto/qat/qat_sym_pmd.h
> +++ b/drivers/crypto/qat/qat_sym_pmd.h
> @@ -15,6 +15,10 @@
>  /** Intel(R) QAT Symmetric Crypto PMD driver name */
>  #define CRYPTODEV_NAME_QAT_SYM_PMD	crypto_qat
> 
> +/* Internal capabilities */
> +#define QAT_SYM_CAP_MIXED_CRYPTO	(1 << 0)
> +#define QAT_SYM_CAP_VALID		(1 << 31)
> +
>  extern uint8_t cryptodev_qat_driver_id;
> 
>  /** private data structure for a QAT device.
> @@ -29,6 +33,7 @@ struct qat_sym_dev_private {
>  	const struct rte_cryptodev_capabilities *qat_dev_capabilities;
>  	/* QAT device symmetric crypto capabilities */
>  	uint16_t min_enq_burst_threshold;
> +	uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
>  };
> 
>  int
> diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
> index 4359f2f0b..bf6af60aa 100644
> --- a/drivers/crypto/qat/qat_sym_session.c
> +++ b/drivers/crypto/qat/qat_sym_session.c
> @@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,
>  }
> 
>  static void
> -qat_sym_session_handle_mixed(struct qat_sym_session *session)
> +qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,
> +		struct qat_sym_session *session)
>  {
> +	const struct qat_sym_dev_private *qat_private = dev->data->dev_private;
> +	enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &
> +			QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;
> +
>  	if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
>  			session->qat_cipher_alg !=
>  			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
> -		session->min_qat_dev_gen = QAT_GEN3;
> +		session->min_qat_dev_gen = min_dev_gen;
>  		qat_sym_session_set_ext_hash_flags(session,
>  			1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);
>  	} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&
>  			session->qat_cipher_alg !=
>  			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
> -		session->min_qat_dev_gen = QAT_GEN3;
> +		session->min_qat_dev_gen = min_dev_gen;
>  		qat_sym_session_set_ext_hash_flags(session,
>  			1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);
>  	} else if ((session->aes_cmac ||
> @@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)
>  			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
>  			session->qat_cipher_alg ==
>  			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {
> -		session->min_qat_dev_gen = QAT_GEN3;
> +		session->min_qat_dev_gen = min_dev_gen;
>  		qat_sym_session_set_ext_hash_flags(session, 0);
>  	}
>  }
> @@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
>  			if (ret < 0)
>  				return ret;
>  			/* Special handling of mixed hash+cipher algorithms */
> -			qat_sym_session_handle_mixed(session);
> +			qat_sym_session_handle_mixed(dev, session);
>  		}
>  		break;
>  	case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
> @@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
>  			if (ret < 0)
>  				return ret;
>  			/* Special handling of mixed hash+cipher algorithms */
> -			qat_sym_session_handle_mixed(session);
> +			qat_sym_session_handle_mixed(dev, session);
>  		}
>  		break;
>  	case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
> --
> 2.17.1

Re: [dpdk-dev] [PATCH 1/2] common/qat: get version of QAT firmware

[Trahe, Fiona]

Hi Adam,

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Thursday, March 12, 2020 2:14 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH 1/2] common/qat: get version of QAT firmware
> 
> This patch adds the function for retrieving QAT firmware
> version, required to check the internal capabilities that
> depend on the FW version.
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> ---
>  drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
>  drivers/common/qat/qat_qp.c             | 89 +++++++++++++++++++++++++
>  drivers/common/qat/qat_qp.h             |  3 +
>  3 files changed, 94 insertions(+)
> 
> diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
> index 1265c2a13..be10fc9bd 100644
> --- a/drivers/common/qat/qat_adf/icp_qat_fw.h
> +++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
> @@ -121,6 +121,8 @@ struct icp_qat_fw_comn_resp {
>  #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
>  #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
>  #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
> +#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
> +#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
> 
>  #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
>  	icp_qat_fw_comn_req_hdr_t.service_type
> diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
> index 9958789f0..93685aeb0 100644
> --- a/drivers/common/qat/qat_qp.c
> +++ b/drivers/common/qat/qat_qp.c
> @@ -19,6 +19,7 @@
>  #include "qat_comp.h"
>  #include "adf_transport_access_macros.h"
> 
> +#define QAT_CQ_MAX_DEQ_RETRIES 10
> 
>  #define ADF_MAX_DESC				4096
>  #define ADF_MIN_DESC				128
> @@ -695,6 +696,94 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
>  	return resp_counter;
>  }
> 
> +/* This is almost same as dequeue_op_burst, without the atomic, without stats
> + * and without the op. Dequeues one response.
> + */
> +static uint8_t
> +qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
> +{
> +	uint8_t result = 0;
> +	uint8_t retries = 0;
> +	struct qat_queue *queue = &(qp->rx_q);
> +	struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
> +			((uint8_t *)queue->base_addr + queue->head);
> +
> +	while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
> +			*(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
> +		/* loop waiting for response until we reach the timeout */
> +		rte_delay_ms(20);
> +	}
> +
> +	if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
> +		/* response received, check status flag */
> +		if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
> +				resp_msg->comn_hdr.comn_status) ==
> +				ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
> +			/* success */
> +			memcpy(out_data, resp_msg, queue->msg_size);
> +			result = 1;
> +		}
> +
[Fiona] Need to distinguish between the case where no response is received (something bad happened - can't use this ring) and an
error response is received - corner case, but could happen in some older fw, so ok to assume the issue is only with
this message and fw is otherwise ok.
So just move the result = 1 outside the bracket and return 0 in out_data in this case. 
 
> +		queue->head = adf_modulo(queue->head + queue->msg_size,
> +				queue->modulo_mask);
> +		rxq_free_desc(qp, queue);
> +	}
> +
> +	return result;
> +}
> +
> +/* Sends a NULL message and extracts QAT fw version from the response.
> + * Used to determine detailed capabilities based on the fw version number.
> + * This assumes that there are no inflight messages, i.e. assumes there's space
> + * on the qp, one message is sent and only one response collected.
> + * Returns fw version number or a negative error code.
[Fiona] update comment to include the 3rd possible outcome - 0 = don't know fw version.
> + */
> +int
> +qat_cq_get_fw_version(struct qat_qp *qp)
> +{
> +	struct qat_queue *queue = &(qp->tx_q);
> +	uint8_t *base_addr = (uint8_t *)queue->base_addr;
> +	struct icp_qat_fw_comn_req null_msg;
> +	struct icp_qat_fw_comn_resp response;
> +
> +	/* prepare the NULL request */
> +	memset(&null_msg, 0, sizeof(null_msg));
> +	null_msg.comn_hdr.hdr_flags =
> +		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
> +	null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
> +	null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
> +
> +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
> +	QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
> +#endif
> +
> +	/* send the NULL request */
> +	memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
> +	queue->tail = adf_modulo(queue->tail + queue->msg_size,
> +			queue->modulo_mask);
> +	txq_write_tail(qp, queue);
> +
> +	/* receive a response */
> +	memset(&response, 0, sizeof(response));
> +	if (qat_cq_dequeue_response(qp, &response)) {
> +
> +#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
> +		QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
> +				sizeof(response));
> +#endif
> +		/* if LW0 bit 24 is set - then the fw version was returned */
> +		if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
> +				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
> +				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
> +			return response.resrvd[0]; /* return LW4 */
> +		else
> +			return 0; /* not set - we don't know fw version */
> +	}
> +
> +	QAT_LOG(ERR, "No response received");
> +	return -EINVAL;
> +}
> +
>  __rte_weak int
>  qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
>  			  void *op_cookie __rte_unused,
> diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
> index 0b95ea3c9..47ad5dd20 100644
> --- a/drivers/common/qat/qat_qp.h
> +++ b/drivers/common/qat/qat_qp.h
> @@ -103,6 +103,9 @@ int
>  qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
>  			enum qat_service_type service);
> 
> +int
> +qat_cq_get_fw_version(struct qat_qp *qp);
> +
>  /* Needed for weak function*/
>  int
>  qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
> --
> 2.17.1

[dpdk-dev] [PATCH v2 0/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch set adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

v2:
* minor fixes and improvements

Adam Dybkowski (2):
  common/qat: get version of QAT firmware
  crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

 doc/guides/cryptodevs/qat.rst           |  9 ++-
 doc/guides/rel_notes/release_20_05.rst  |  7 ++
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 92 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 drivers/crypto/qat/qat_sym_pmd.c        | 27 ++++++++
 drivers/crypto/qat/qat_sym_pmd.h        |  5 ++
 drivers/crypto/qat/qat_sym_session.c    | 17 +++--
 8 files changed, 151 insertions(+), 11 deletions(-)

-- 
2.17.1

[dpdk-dev] [PATCH v2 1/2] common/qat: get version of QAT firmware

[Adam Dybkowski]

This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 92 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 3 files changed, 97 insertions(+)

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 1265c2a13..be10fc9bd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -121,6 +121,8 @@ struct icp_qat_fw_comn_resp {
 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
 
 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
 	icp_qat_fw_comn_req_hdr_t.service_type
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 9958789f0..5c4c6fa5d 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -19,6 +19,7 @@
 #include "qat_comp.h"
 #include "adf_transport_access_macros.h"
 
+#define QAT_CQ_MAX_DEQ_RETRIES 10
 
 #define ADF_MAX_DESC				4096
 #define ADF_MIN_DESC				128
@@ -695,6 +696,97 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 	return resp_counter;
 }
 
+/* This is almost same as dequeue_op_burst, without the atomic, without stats
+ * and without the op. Dequeues one response.
+ */
+static uint8_t
+qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
+{
+	uint8_t result = 0;
+	uint8_t retries = 0;
+	struct qat_queue *queue = &(qp->rx_q);
+	struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
+			((uint8_t *)queue->base_addr + queue->head);
+
+	while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
+			*(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
+		/* loop waiting for response until we reach the timeout */
+		rte_delay_ms(20);
+	}
+
+	if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
+		/* response received */
+		result = 1;
+
+		/* check status flag */
+		if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
+				resp_msg->comn_hdr.comn_status) ==
+				ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+			/* success */
+			memcpy(out_data, resp_msg, queue->msg_size);
+		} else {
+			memset(out_data, 0, queue->msg_size);
+		}
+
+		queue->head = adf_modulo(queue->head + queue->msg_size,
+				queue->modulo_mask);
+		rxq_free_desc(qp, queue);
+	}
+
+	return result;
+}
+
+/* Sends a NULL message and extracts QAT fw version from the response.
+ * Used to determine detailed capabilities based on the fw version number.
+ * This assumes that there are no inflight messages, i.e. assumes there's space
+ * on the qp, one message is sent and only one response collected.
+ * Returns fw version number or 0 for unknown version or a negative error code.
+ */
+int
+qat_cq_get_fw_version(struct qat_qp *qp)
+{
+	struct qat_queue *queue = &(qp->tx_q);
+	uint8_t *base_addr = (uint8_t *)queue->base_addr;
+	struct icp_qat_fw_comn_req null_msg;
+	struct icp_qat_fw_comn_resp response;
+
+	/* prepare the NULL request */
+	memset(&null_msg, 0, sizeof(null_msg));
+	null_msg.comn_hdr.hdr_flags =
+		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+	null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+	null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+	QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
+#endif
+
+	/* send the NULL request */
+	memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
+	queue->tail = adf_modulo(queue->tail + queue->msg_size,
+			queue->modulo_mask);
+	txq_write_tail(qp, queue);
+
+	/* receive a response */
+	if (qat_cq_dequeue_response(qp, &response)) {
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+		QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
+				sizeof(response));
+#endif
+		/* if LW0 bit 24 is set - then the fw version was returned */
+		if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
+			return response.resrvd[0]; /* return LW4 */
+		else
+			return 0; /* not set - we don't know fw version */
+	}
+
+	QAT_LOG(ERR, "No response received");
+	return -EINVAL;
+}
+
 __rte_weak int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
 			  void *op_cookie __rte_unused,
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 0b95ea3c9..47ad5dd20 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,6 +103,9 @@ int
 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 			enum qat_service_type service);
 
+int
+qat_cq_get_fw_version(struct qat_qp *qp);
+
 /* Needed for weak function*/
 int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
-- 
2.17.1

[dpdk-dev] [PATCH v2 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 doc/guides/cryptodevs/qat.rst          |  9 ++++-----
 doc/guides/rel_notes/release_20_05.rst |  7 +++++++
 drivers/crypto/qat/qat_sym_pmd.c       | 27 ++++++++++++++++++++++++++
 drivers/crypto/qat/qat_sym_pmd.h       |  5 +++++
 drivers/crypto/qat/qat_sym_session.c   | 17 ++++++++++------
 5 files changed, 54 insertions(+), 11 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 06985e319..2e0dc1b00 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:
    +------------------+-----------+-------------+----------+----------+
    | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
    +==================+===========+=============+==========+==========+
-   | NULL CIPHER      | Y         | 3           | 3        | Y        |
+   | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
-   | SNOW3G UEA2      | 3         | Y           | 3        | 3        |
+   | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | ZUC EEA3         | 3         | 3           | 2&3      | 3        |
+   | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | AES CTR          | Y         | 3           | 3        | Y        |
+   | AES CTR          | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
 
 * The combinations marked as "Y" are supported on all QAT hardware versions.
 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
-* The combinations marked as "3" are supported on GEN3 QAT hardware only.
 
 
 Limitations
diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 2190eaf85..bdfa64973 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -56,6 +56,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
+
+  Enabled handling of mixed algorithms in encrypted digest hash-cipher
+  (generation) and cipher-hash (verification) requests in QAT PMD
+  when running on GEN2 QAT hardware with particular firmware versions
+  (GEN3 support was added in DPDK 20.02).
+
 
 Removed Items
 -------------
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 666ede726..41305ea56 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -14,6 +14,8 @@
 #include "qat_sym_session.h"
 #include "qat_sym_pmd.h"
 
+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
+
 uint8_t cryptodev_qat_driver_id;
 
 static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
@@ -187,6 +189,31 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 				qat_sgl_dst);
 	}
 
+	/* Get fw version from QAT (GEN2), skip if we've got it already */
+	if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities
+			& QAT_SYM_CAP_VALID)) {
+		ret = qat_cq_get_fw_version(qp);
+
+		if (ret < 0) {
+			qat_sym_qp_release(dev, qp_id);
+			return ret;
+		}
+
+		if (ret != 0)
+			QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
+					(ret >> 24) & 0xff,
+					(ret >> 16) & 0xff,
+					(ret >> 8) & 0xff);
+		else
+			QAT_LOG(DEBUG, "unknown QAT firmware version");
+
+		/* set capabilities based on the fw version */
+		qat_private->internal_capabilities = QAT_SYM_CAP_VALID |
+				((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
+						QAT_SYM_CAP_MIXED_CRYPTO : 0);
+		ret = 0;
+	}
+
 	return ret;
 }
 
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index a32c25abc..a5a31e512 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -15,6 +15,10 @@
 /** Intel(R) QAT Symmetric Crypto PMD driver name */
 #define CRYPTODEV_NAME_QAT_SYM_PMD	crypto_qat
 
+/* Internal capabilities */
+#define QAT_SYM_CAP_MIXED_CRYPTO	(1 << 0)
+#define QAT_SYM_CAP_VALID		(1 << 31)
+
 extern uint8_t cryptodev_qat_driver_id;
 
 /** private data structure for a QAT device.
@@ -29,6 +33,7 @@ struct qat_sym_dev_private {
 	const struct rte_cryptodev_capabilities *qat_dev_capabilities;
 	/* QAT device symmetric crypto capabilities */
 	uint16_t min_enq_burst_threshold;
+	uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
 };
 
 int
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 4359f2f0b..bf6af60aa 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,
 }
 
 static void
-qat_sym_session_handle_mixed(struct qat_sym_session *session)
+qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,
+		struct qat_sym_session *session)
 {
+	const struct qat_sym_dev_private *qat_private = dev->data->dev_private;
+	enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &
+			QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;
+
 	if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);
 	} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);
 	} else if ((session->aes_cmac ||
@@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 			session->qat_cipher_alg ==
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session, 0);
 	}
 }
@@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
@@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
-- 
2.17.1

[dpdk-dev] [PATCH v3 0/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch set adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

v2:
* minor fixes and improvements

v3:
* include missing header file

Adam Dybkowski (2):
  common/qat: get version of QAT firmware
  crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

 doc/guides/cryptodevs/qat.rst           |  9 ++-
 doc/guides/rel_notes/release_20_05.rst  |  7 ++
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 93 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 drivers/crypto/qat/qat_sym_pmd.c        | 27 +++++++
 drivers/crypto/qat/qat_sym_pmd.h        |  5 ++
 drivers/crypto/qat/qat_sym_session.c    | 17 +++--
 8 files changed, 152 insertions(+), 11 deletions(-)

-- 
2.17.1

[dpdk-dev] [PATCH v3 1/2] common/qat: get version of QAT firmware

[Adam Dybkowski]

This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 93 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 3 files changed, 98 insertions(+)

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 1265c2a13..be10fc9bd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -121,6 +121,8 @@ struct icp_qat_fw_comn_resp {
 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
 
 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
 	icp_qat_fw_comn_req_hdr_t.service_type
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 9958789f0..67daa736c 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -3,6 +3,7 @@
  */
 
 #include <rte_common.h>
+#include <rte_cycles.h>
 #include <rte_dev.h>
 #include <rte_malloc.h>
 #include <rte_memzone.h>
@@ -19,6 +20,7 @@
 #include "qat_comp.h"
 #include "adf_transport_access_macros.h"
 
+#define QAT_CQ_MAX_DEQ_RETRIES 10
 
 #define ADF_MAX_DESC				4096
 #define ADF_MIN_DESC				128
@@ -695,6 +697,97 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 	return resp_counter;
 }
 
+/* This is almost same as dequeue_op_burst, without the atomic, without stats
+ * and without the op. Dequeues one response.
+ */
+static uint8_t
+qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
+{
+	uint8_t result = 0;
+	uint8_t retries = 0;
+	struct qat_queue *queue = &(qp->rx_q);
+	struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
+			((uint8_t *)queue->base_addr + queue->head);
+
+	while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
+			*(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
+		/* loop waiting for response until we reach the timeout */
+		rte_delay_ms(20);
+	}
+
+	if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
+		/* response received */
+		result = 1;
+
+		/* check status flag */
+		if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
+				resp_msg->comn_hdr.comn_status) ==
+				ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+			/* success */
+			memcpy(out_data, resp_msg, queue->msg_size);
+		} else {
+			memset(out_data, 0, queue->msg_size);
+		}
+
+		queue->head = adf_modulo(queue->head + queue->msg_size,
+				queue->modulo_mask);
+		rxq_free_desc(qp, queue);
+	}
+
+	return result;
+}
+
+/* Sends a NULL message and extracts QAT fw version from the response.
+ * Used to determine detailed capabilities based on the fw version number.
+ * This assumes that there are no inflight messages, i.e. assumes there's space
+ * on the qp, one message is sent and only one response collected.
+ * Returns fw version number or 0 for unknown version or a negative error code.
+ */
+int
+qat_cq_get_fw_version(struct qat_qp *qp)
+{
+	struct qat_queue *queue = &(qp->tx_q);
+	uint8_t *base_addr = (uint8_t *)queue->base_addr;
+	struct icp_qat_fw_comn_req null_msg;
+	struct icp_qat_fw_comn_resp response;
+
+	/* prepare the NULL request */
+	memset(&null_msg, 0, sizeof(null_msg));
+	null_msg.comn_hdr.hdr_flags =
+		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+	null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+	null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+	QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
+#endif
+
+	/* send the NULL request */
+	memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
+	queue->tail = adf_modulo(queue->tail + queue->msg_size,
+			queue->modulo_mask);
+	txq_write_tail(qp, queue);
+
+	/* receive a response */
+	if (qat_cq_dequeue_response(qp, &response)) {
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+		QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
+				sizeof(response));
+#endif
+		/* if LW0 bit 24 is set - then the fw version was returned */
+		if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
+			return response.resrvd[0]; /* return LW4 */
+		else
+			return 0; /* not set - we don't know fw version */
+	}
+
+	QAT_LOG(ERR, "No response received");
+	return -EINVAL;
+}
+
 __rte_weak int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
 			  void *op_cookie __rte_unused,
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 0b95ea3c9..47ad5dd20 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -103,6 +103,9 @@ int
 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 			enum qat_service_type service);
 
+int
+qat_cq_get_fw_version(struct qat_qp *qp);
+
 /* Needed for weak function*/
 int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
-- 
2.17.1

[dpdk-dev] [PATCH v3 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 doc/guides/cryptodevs/qat.rst          |  9 ++++-----
 doc/guides/rel_notes/release_20_05.rst |  7 +++++++
 drivers/crypto/qat/qat_sym_pmd.c       | 27 ++++++++++++++++++++++++++
 drivers/crypto/qat/qat_sym_pmd.h       |  5 +++++
 drivers/crypto/qat/qat_sym_session.c   | 17 ++++++++++------
 5 files changed, 54 insertions(+), 11 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 06985e319..2e0dc1b00 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:
    +------------------+-----------+-------------+----------+----------+
    | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
    +==================+===========+=============+==========+==========+
-   | NULL CIPHER      | Y         | 3           | 3        | Y        |
+   | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
-   | SNOW3G UEA2      | 3         | Y           | 3        | 3        |
+   | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | ZUC EEA3         | 3         | 3           | 2&3      | 3        |
+   | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | AES CTR          | Y         | 3           | 3        | Y        |
+   | AES CTR          | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
 
 * The combinations marked as "Y" are supported on all QAT hardware versions.
 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
-* The combinations marked as "3" are supported on GEN3 QAT hardware only.
 
 
 Limitations
diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 2190eaf85..bdfa64973 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -56,6 +56,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =========================================================
 
+* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
+
+  Enabled handling of mixed algorithms in encrypted digest hash-cipher
+  (generation) and cipher-hash (verification) requests in QAT PMD
+  when running on GEN2 QAT hardware with particular firmware versions
+  (GEN3 support was added in DPDK 20.02).
+
 
 Removed Items
 -------------
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 666ede726..41305ea56 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -14,6 +14,8 @@
 #include "qat_sym_session.h"
 #include "qat_sym_pmd.h"
 
+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
+
 uint8_t cryptodev_qat_driver_id;
 
 static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
@@ -187,6 +189,31 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 				qat_sgl_dst);
 	}
 
+	/* Get fw version from QAT (GEN2), skip if we've got it already */
+	if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities
+			& QAT_SYM_CAP_VALID)) {
+		ret = qat_cq_get_fw_version(qp);
+
+		if (ret < 0) {
+			qat_sym_qp_release(dev, qp_id);
+			return ret;
+		}
+
+		if (ret != 0)
+			QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
+					(ret >> 24) & 0xff,
+					(ret >> 16) & 0xff,
+					(ret >> 8) & 0xff);
+		else
+			QAT_LOG(DEBUG, "unknown QAT firmware version");
+
+		/* set capabilities based on the fw version */
+		qat_private->internal_capabilities = QAT_SYM_CAP_VALID |
+				((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
+						QAT_SYM_CAP_MIXED_CRYPTO : 0);
+		ret = 0;
+	}
+
 	return ret;
 }
 
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index a32c25abc..a5a31e512 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -15,6 +15,10 @@
 /** Intel(R) QAT Symmetric Crypto PMD driver name */
 #define CRYPTODEV_NAME_QAT_SYM_PMD	crypto_qat
 
+/* Internal capabilities */
+#define QAT_SYM_CAP_MIXED_CRYPTO	(1 << 0)
+#define QAT_SYM_CAP_VALID		(1 << 31)
+
 extern uint8_t cryptodev_qat_driver_id;
 
 /** private data structure for a QAT device.
@@ -29,6 +33,7 @@ struct qat_sym_dev_private {
 	const struct rte_cryptodev_capabilities *qat_dev_capabilities;
 	/* QAT device symmetric crypto capabilities */
 	uint16_t min_enq_burst_threshold;
+	uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
 };
 
 int
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 4359f2f0b..bf6af60aa 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -459,18 +459,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,
 }
 
 static void
-qat_sym_session_handle_mixed(struct qat_sym_session *session)
+qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,
+		struct qat_sym_session *session)
 {
+	const struct qat_sym_dev_private *qat_private = dev->data->dev_private;
+	enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &
+			QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;
+
 	if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);
 	} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);
 	} else if ((session->aes_cmac ||
@@ -479,7 +484,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 			session->qat_cipher_alg ==
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session, 0);
 	}
 }
@@ -532,7 +537,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
@@ -551,7 +556,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
-- 
2.17.1

[dpdk-dev] [PATCH v4 0/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch set adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

v2:
* minor fixes and improvements

v3:
* include missing header file

v4:
* update documentation

Adam Dybkowski (2):
  common/qat: get version of QAT firmware
  crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

 doc/guides/cryptodevs/qat.rst           | 13 ++--
 doc/guides/rel_notes/release_20_05.rst  |  7 ++
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 93 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 drivers/crypto/qat/qat_sym_pmd.c        | 27 +++++++
 drivers/crypto/qat/qat_sym_pmd.h        |  5 ++
 drivers/crypto/qat/qat_sym_session.c    | 17 +++--
 8 files changed, 156 insertions(+), 11 deletions(-)

-- 
2.17.1

[dpdk-dev] [PATCH v4 1/2] common/qat: get version of QAT firmware

[Adam Dybkowski]

This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 drivers/common/qat/qat_adf/icp_qat_fw.h |  2 +
 drivers/common/qat/qat_qp.c             | 93 +++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h             |  3 +
 3 files changed, 98 insertions(+)

diff --git a/drivers/common/qat/qat_adf/icp_qat_fw.h b/drivers/common/qat/qat_adf/icp_qat_fw.h
index 1265c2a13..be10fc9bd 100644
--- a/drivers/common/qat/qat_adf/icp_qat_fw.h
+++ b/drivers/common/qat/qat_adf/icp_qat_fw.h
@@ -121,6 +121,8 @@ struct icp_qat_fw_comn_resp {
 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS 0
+#define ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK 0x1
 
 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
 	icp_qat_fw_comn_req_hdr_t.service_type
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b0a206434..eb1da7243 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -3,6 +3,7 @@
  */
 
 #include <rte_common.h>
+#include <rte_cycles.h>
 #include <rte_dev.h>
 #include <rte_malloc.h>
 #include <rte_memzone.h>
@@ -19,6 +20,7 @@
 #include "qat_comp.h"
 #include "adf_transport_access_macros.h"
 
+#define QAT_CQ_MAX_DEQ_RETRIES 10
 
 #define ADF_MAX_DESC				4096
 #define ADF_MIN_DESC				128
@@ -698,6 +700,97 @@ qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 	return resp_counter;
 }
 
+/* This is almost same as dequeue_op_burst, without the atomic, without stats
+ * and without the op. Dequeues one response.
+ */
+static uint8_t
+qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
+{
+	uint8_t result = 0;
+	uint8_t retries = 0;
+	struct qat_queue *queue = &(qp->rx_q);
+	struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
+			((uint8_t *)queue->base_addr + queue->head);
+
+	while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
+			*(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
+		/* loop waiting for response until we reach the timeout */
+		rte_delay_ms(20);
+	}
+
+	if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
+		/* response received */
+		result = 1;
+
+		/* check status flag */
+		if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
+				resp_msg->comn_hdr.comn_status) ==
+				ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
+			/* success */
+			memcpy(out_data, resp_msg, queue->msg_size);
+		} else {
+			memset(out_data, 0, queue->msg_size);
+		}
+
+		queue->head = adf_modulo(queue->head + queue->msg_size,
+				queue->modulo_mask);
+		rxq_free_desc(qp, queue);
+	}
+
+	return result;
+}
+
+/* Sends a NULL message and extracts QAT fw version from the response.
+ * Used to determine detailed capabilities based on the fw version number.
+ * This assumes that there are no inflight messages, i.e. assumes there's space
+ * on the qp, one message is sent and only one response collected.
+ * Returns fw version number or 0 for unknown version or a negative error code.
+ */
+int
+qat_cq_get_fw_version(struct qat_qp *qp)
+{
+	struct qat_queue *queue = &(qp->tx_q);
+	uint8_t *base_addr = (uint8_t *)queue->base_addr;
+	struct icp_qat_fw_comn_req null_msg;
+	struct icp_qat_fw_comn_resp response;
+
+	/* prepare the NULL request */
+	memset(&null_msg, 0, sizeof(null_msg));
+	null_msg.comn_hdr.hdr_flags =
+		ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
+	null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
+	null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+	QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
+#endif
+
+	/* send the NULL request */
+	memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
+	queue->tail = adf_modulo(queue->tail + queue->msg_size,
+			queue->modulo_mask);
+	txq_write_tail(qp, queue);
+
+	/* receive a response */
+	if (qat_cq_dequeue_response(qp, &response)) {
+
+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
+		QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
+				sizeof(response));
+#endif
+		/* if LW0 bit 24 is set - then the fw version was returned */
+		if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
+				ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
+			return response.resrvd[0]; /* return LW4 */
+		else
+			return 0; /* not set - we don't know fw version */
+	}
+
+	QAT_LOG(ERR, "No response received");
+	return -EINVAL;
+}
+
 __rte_weak int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
 			  void *op_cookie __rte_unused,
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 0d6896d7b..88d3c9942 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -104,6 +104,9 @@ int
 qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 			enum qat_service_type service);
 
+int
+qat_cq_get_fw_version(struct qat_qp *qp);
+
 /* Needed for weak function*/
 int
 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
-- 
2.17.1

Re: [dpdk-dev] [PATCH v4 1/2] common/qat: get version of QAT firmware

[Trahe, Fiona]

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Thursday, March 26, 2020 4:22 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH v4 1/2] common/qat: get version of QAT firmware
> 
> This patch adds the function for retrieving QAT firmware
> version, required to check the internal capabilities that
> depend on the FW version.
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

Re: [dpdk-dev] [PATCH v4 1/2] common/qat: get version of QAT firmware

[Akhil Goyal]

> 
> > -----Original Message-----
> > From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> > Sent: Thursday, March 26, 2020 4:22 PM
> > To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>;
> akhil.goyal@nxp.com
> > Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> > Subject: [PATCH v4 1/2] common/qat: get version of QAT firmware
> >
> > This patch adds the function for retrieving QAT firmware
> > version, required to check the internal capabilities that
> > depend on the FW version.
> >
> > Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
> Acked-by: Fiona Trahe <fiona.trahe@intel.com>

Applied to dpdk-next-crypto

Thanks.

[dpdk-dev] [PATCH v4 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Adam Dybkowski]

This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
---
 doc/guides/cryptodevs/qat.rst          | 13 ++++++++-----
 doc/guides/rel_notes/release_20_05.rst |  7 +++++++
 drivers/crypto/qat/qat_sym_pmd.c       | 27 ++++++++++++++++++++++++++
 drivers/crypto/qat/qat_sym_pmd.h       |  5 +++++
 drivers/crypto/qat/qat_sym_session.c   | 17 ++++++++++------
 5 files changed, 58 insertions(+), 11 deletions(-)

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 1e83ed626..c79e686de 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -82,18 +82,17 @@ All the usual chains are supported and also some mixed chains:
    +------------------+-----------+-------------+----------+----------+
    | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
    +==================+===========+=============+==========+==========+
-   | NULL CIPHER      | Y         | 3           | 3        | Y        |
+   | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
-   | SNOW3G UEA2      | 3         | Y           | 3        | 3        |
+   | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | ZUC EEA3         | 3         | 3           | 2&3      | 3        |
+   | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
    +------------------+-----------+-------------+----------+----------+
-   | AES CTR          | Y         | 3           | 3        | Y        |
+   | AES CTR          | Y         | 2&3         | 2&3      | Y        |
    +------------------+-----------+-------------+----------+----------+
 
 * The combinations marked as "Y" are supported on all QAT hardware versions.
 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
-* The combinations marked as "3" are supported on GEN3 QAT hardware only.
 
 
 Limitations
@@ -120,6 +119,8 @@ Limitations
   enqueued to the device and will be marked as failed. The simplest way to
   mitigate this is to use the bdf whitelist to avoid mixing devices of different
   generations in the same process if planning to use for GCM.
+* The mixed algo feature on GEN2 is not supported by all kernel drivers. Check
+  the notes under the Available Kernel Drivers table below for specific details.
 
 Extra notes on KASUMI F9
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -379,6 +380,8 @@ to see the full table)
    | Yes | No  | No  | 3   | P5xxx    | p             | qat_p5xxx     | p5xxx      | 18a0   | 1    | 18a1   | 128    |
    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 
+* Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 01.org driver version 4.9.0+
+
 The first 3 columns indicate the service:
 
 * S = Symmetric crypto service (via cryptodev API)
diff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst
index 1dfcfccee..fe3e649d5 100644
--- a/doc/guides/rel_notes/release_20_05.rst
+++ b/doc/guides/rel_notes/release_20_05.rst
@@ -70,6 +70,13 @@ New Features
   by making use of the event device capabilities. The event mode currently supports
   only inline IPsec protocol offload.
 
+* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
+
+  Enabled handling of mixed algorithms in encrypted digest hash-cipher
+  (generation) and cipher-hash (verification) requests in QAT PMD
+  when running on GEN2 QAT hardware with particular firmware versions
+  (GEN3 support was added in DPDK 20.02).
+
 
 Removed Items
 -------------
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index 50abdf6f5..e887c880f 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -14,6 +14,8 @@
 #include "qat_sym_session.h"
 #include "qat_sym_pmd.h"
 
+#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
+
 uint8_t cryptodev_qat_driver_id;
 
 static const struct rte_cryptodev_capabilities qat_gen1_sym_capabilities[] = {
@@ -187,6 +189,31 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 				qat_sgl_dst);
 	}
 
+	/* Get fw version from QAT (GEN2), skip if we've got it already */
+	if (qp->qat_dev_gen == QAT_GEN2 && !(qat_private->internal_capabilities
+			& QAT_SYM_CAP_VALID)) {
+		ret = qat_cq_get_fw_version(qp);
+
+		if (ret < 0) {
+			qat_sym_qp_release(dev, qp_id);
+			return ret;
+		}
+
+		if (ret != 0)
+			QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
+					(ret >> 24) & 0xff,
+					(ret >> 16) & 0xff,
+					(ret >> 8) & 0xff);
+		else
+			QAT_LOG(DEBUG, "unknown QAT firmware version");
+
+		/* set capabilities based on the fw version */
+		qat_private->internal_capabilities = QAT_SYM_CAP_VALID |
+				((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
+						QAT_SYM_CAP_MIXED_CRYPTO : 0);
+		ret = 0;
+	}
+
 	return ret;
 }
 
diff --git a/drivers/crypto/qat/qat_sym_pmd.h b/drivers/crypto/qat/qat_sym_pmd.h
index a32c25abc..a5a31e512 100644
--- a/drivers/crypto/qat/qat_sym_pmd.h
+++ b/drivers/crypto/qat/qat_sym_pmd.h
@@ -15,6 +15,10 @@
 /** Intel(R) QAT Symmetric Crypto PMD driver name */
 #define CRYPTODEV_NAME_QAT_SYM_PMD	crypto_qat
 
+/* Internal capabilities */
+#define QAT_SYM_CAP_MIXED_CRYPTO	(1 << 0)
+#define QAT_SYM_CAP_VALID		(1 << 31)
+
 extern uint8_t cryptodev_qat_driver_id;
 
 /** private data structure for a QAT device.
@@ -29,6 +33,7 @@ struct qat_sym_dev_private {
 	const struct rte_cryptodev_capabilities *qat_dev_capabilities;
 	/* QAT device symmetric crypto capabilities */
 	uint16_t min_enq_burst_threshold;
+	uint32_t internal_capabilities; /* see flags QAT_SYM_CAP_xxx */
 };
 
 int
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 61ab9edc4..fd2cc382e 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -464,18 +464,23 @@ qat_sym_session_set_ext_hash_flags(struct qat_sym_session *session,
 }
 
 static void
-qat_sym_session_handle_mixed(struct qat_sym_session *session)
+qat_sym_session_handle_mixed(const struct rte_cryptodev *dev,
+		struct qat_sym_session *session)
 {
+	const struct qat_sym_dev_private *qat_private = dev->data->dev_private;
+	enum qat_device_gen min_dev_gen = (qat_private->internal_capabilities &
+			QAT_SYM_CAP_MIXED_CRYPTO) ? QAT_GEN2 : QAT_GEN3;
+
 	if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS);
 	} else if (session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 &&
 			session->qat_cipher_alg !=
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session,
 			1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS);
 	} else if ((session->aes_cmac ||
@@ -484,7 +489,7 @@ qat_sym_session_handle_mixed(struct qat_sym_session *session)
 			ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 			session->qat_cipher_alg ==
 			ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {
-		session->min_qat_dev_gen = QAT_GEN3;
+		session->min_qat_dev_gen = min_dev_gen;
 		qat_sym_session_set_ext_hash_flags(session, 0);
 	}
 }
@@ -537,7 +542,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
@@ -556,7 +561,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev,
 			if (ret < 0)
 				return ret;
 			/* Special handling of mixed hash+cipher algorithms */
-			qat_sym_session_handle_mixed(session);
+			qat_sym_session_handle_mixed(dev, session);
 		}
 		break;
 	case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
-- 
2.17.1

Re: [dpdk-dev] [PATCH v4 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT

[Trahe, Fiona]

> -----Original Message-----
> From: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Sent: Thursday, March 26, 2020 4:22 PM
> To: dev@dpdk.org; Trahe, Fiona <fiona.trahe@intel.com>; akhil.goyal@nxp.com
> Cc: Dybkowski, AdamX <adamx.dybkowski@intel.com>
> Subject: [PATCH v4 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT
> 
> This patch adds handling of mixed hash-cipher algorithms
> available on GEN2 QAT in particular firmware versions.
> Also the documentation is updated to show the mixed crypto
> algorithms are supported on QAT GEN2.
> 
> Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>