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Wed, 23 Oct 2019 13:51:23 +0000 Received: from VE1PR04MB6639.eurprd04.prod.outlook.com ([fe80::9dc:aa5c:2bb8:b561]) by VE1PR04MB6639.eurprd04.prod.outlook.com ([fe80::9dc:aa5c:2bb8:b561%6]) with mapi id 15.20.2367.022; Wed, 23 Oct 2019 13:51:23 +0000 From: Akhil Goyal To: Nicolas Chautru , "dev@dpdk.org" CC: "ferruh.yigit@intel.com" , "thomas@monjalon.net" Thread-Topic: [PATCH v2 0/2] baseband/fpga_lte_fec: bug fixes from FPGA LTE HW validation Thread-Index: AQHViRZlilMjKs0SXEW3RHBwkd1IbKdoP6BA Date: Wed, 23 Oct 2019 13:51:23 +0000 Message-ID: References: <1571750177-387063-1-git-send-email-nicolas.chautru@intel.com> In-Reply-To: <1571750177-387063-1-git-send-email-nicolas.chautru@intel.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=akhil.goyal@nxp.com; x-originating-ip: [92.120.1.65] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: e48ca0f7-c9ca-4164-dad4-08d757c01769 x-ms-traffictypediagnostic: VE1PR04MB6447: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e48ca0f7-c9ca-4164-dad4-08d757c01769 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Oct 2019 13:51:23.2736 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9A1+ixt8KkrcCOxkRzDz7zvklYAFWafij6KRUpknqUFuC9pxMRHGEM1Q0mFCGVpGZz3OLR05Yz5Ktd8cqGHw3A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6447 Subject: Re: [dpdk-dev] [PATCH v2 0/2] baseband/fpga_lte_fec: bug fixes from FPGA LTE HW validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Failures found when running validation with FPGA HW and the related FPGA = PMD > driver on latest code base pre 19.11. >=20 > v2: Adding Fixes: and cc: stable to commit messages. (There is no Bugzill= a Id for > these) >=20 > Two bug fixes below : > - The first error is a fatal failure during probing which was missed and = would > fundamentally prevent using the driver. This was missed as HW validation = was > still focus on old DPDK release. The assumptions had change on driver > assignment during probing and the impact was missed so far. > - The 2nd failure is not as critical but good to fix as it can cause spur= ious > detection of flushing failure. > (Resending as previous one did not seem to go through on dpdk ml). >=20 >=20 > Nic Chautru (2): > baseband/fpga_lte_fec: fix probing fatal failure > baseband/fpga_lte_fec: fix to polling of MMIO register >=20 > drivers/baseband/fpga_lte_fec/fpga_lte_fec.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 Applied to dpdk-next-crypto Thanks.