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Wed, 25 Mar 2020 09:10:18 +0000 Received: from VE1PR04MB6639.eurprd04.prod.outlook.com ([fe80::8060:a35c:4858:c490]) by VE1PR04MB6639.eurprd04.prod.outlook.com ([fe80::8060:a35c:4858:c490%7]) with mapi id 15.20.2835.023; Wed, 25 Mar 2020 09:10:18 +0000 From: Akhil Goyal To: Nagadheeraj Rottela , "thomas@monjalon.net" CC: "dev@dpdk.org" , "jsrikanth@marvell.com" Thread-Topic: [PATCH v2 1/2] crypto/nitrox: fix invalid CSR register address generation Thread-Index: AQHV68CF/rNBkDG79Uavfc6QEnkUi6hZMn4g Date: Wed, 25 Mar 2020 09:10:17 +0000 Message-ID: References: <20200220110431.30074-1-rnagadheeraj@marvell.com> <20200225094642.29239-1-rnagadheeraj@marvell.com> In-Reply-To: <20200225094642.29239-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=akhil.goyal@nxp.com; x-originating-ip: [45.118.166.92] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 2baf2e74-1a03-4727-1653-08d7d09c568c x-ms-traffictypediagnostic: VE1PR04MB6446: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4502; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2baf2e74-1a03-4727-1653-08d7d09c568c X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Mar 2020 09:10:18.0452 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 6rd+U84O0DChvWb+Yclwp7JNnplil5OszPm+ogCJO6EnvnsMQmcgmkeMg9RgJCPfzY9u2SZx9gJ/FHI37xUOjw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6446 Subject: Re: [dpdk-dev] [PATCH v2 1/2] crypto/nitrox: fix invalid CSR register address generation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will > evaluate to incorrect values due to unintended sign extension from int > to unsigned long. To fix this, add UL suffix to the constants in these > macros. >=20 > Coverity issue: 349899, 349905, 349911, 349921, 349923 >=20 > Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management") >=20 > Signed-off-by: Nagadheeraj Rottela > --- > drivers/crypto/nitrox/nitrox_csr.h | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/crypto/nitrox/nitrox_csr.h > b/drivers/crypto/nitrox/nitrox_csr.h > index 8cd92e38b..b4c969b26 100644 > --- a/drivers/crypto/nitrox/nitrox_csr.h > +++ b/drivers/crypto/nitrox/nitrox_csr.h > @@ -12,15 +12,15 @@ > #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset)) >=20 > /* NPS packet registers */ > -#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) > -#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) > -#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) > -#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) > -#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) > -#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) > -#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) > -#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) > -#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) > +#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) > +#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * > 0x40000UL)) > +#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) > +#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) > +#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * > 0x40000UL)) > +#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * > 0x40000UL)) > +#define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) > +#define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * > 0x40000UL)) > +#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) >=20 > /* AQM Virtual Function Registers */ > #define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) AQMQ_QSZX may also need to be updated.