From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 7551BA046B for ; Mon, 24 Jun 2019 17:29:11 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 432621BCDE; Mon, 24 Jun 2019 17:29:11 +0200 (CEST) Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-eopbgr60065.outbound.protection.outlook.com [40.107.6.65]) by dpdk.org (Postfix) with ESMTP id 53CEC1BCD4 for ; Mon, 24 Jun 2019 17:29:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SGq7L2DehrMz08tkdgWSEXFYkG2oNiBPf/2Z3feUWFc=; b=RyEtEN7adWLJGm2Jn8rFhfk24vMHk1ukfZHynHdA+rfG+0iAkHJG65v5hAtF8gJCBJQYqFgJwKO1baPsr6r/loLuyvkE6nVTrmkyALo693byNDOdWA1ux9vSwseDusaF4il6wRJmtXRRPazuQlqeDHjtkU/PRpImg3IAA10Cdhc= Received: from VE1PR08MB4640.eurprd08.prod.outlook.com (10.255.27.75) by VE1PR08MB5165.eurprd08.prod.outlook.com (20.179.30.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5165; H:VE1PR08MB4640.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: qGXx25DsDl8QmQNbm7APv9f4dg6VxOTS3RC8qCEq2JIIpO9m59qLbsLMKAGYAO2vawmuzkGd6ihqG8BezJn6TcFyXfbANXBZrZWyf59QhHO32Eguz84W9rVp7pYxzJDcfrXvkDT58sY2UdtGnMdPWwCqYQWA07vrfL1PMjD5xJnf4WIQafnnEESNWLVkGrbDZkn46bTNQ1o8RMTIyyYm8uqHZRYrDQ1tGovKMJemjW3e52/c88BwZzD700fY9S233xcdPiPRfszjZxzpNaBponT0Pmw9AJgITPgXhWz4iRdwHpVdrITA5YIiA9xeI5rG/Y++48ivbruEtjIxBOtym//xNElTdTAWuPkFev270ZvBkFiHD3YOlfbux+hj/fXD/FfrpLQsXvnTMrsrk1cZaoTN6jN3IVpczYtxp/WI/kA= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5b1670e8-66f0-499a-69d0-08d6f8b8b305 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 15:29:07.9062 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Phil.Yang@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5165 Subject: Re: [dpdk-dev] [PATCH v2 2/3] test/atomic: add 128b compare and swap test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Eads, Gage > Sent: Monday, June 24, 2019 11:10 PM > To: Phil Yang (Arm Technology China) ; dev@dpdk.org > Cc: thomas@monjalon.net; jerinj@marvell.com; hemant.agrawal@nxp.com; > Honnappa Nagarahalli ; Gavin Hu (Arm > Technology China) ; nd > Subject: RE: [PATCH v2 2/3] test/atomic: add 128b compare and swap test >=20 > Hi Phil, >=20 > Looks good overall, just a few documentation issues. >=20 > >=20 > > + * > > + * - Test "128b compare and swap" (aarch64 and x86_64 only) > > + * > > + * - Initialize 128-bit atomic variables to zero. > > + * > > + * - Invoke ``test_atomici128_cmp_exchange()`` on each lcore. Before > > doing > > + * anything else, the cores are waiting a synchro. Each lcore does > > + * these compare and swap (CAS) operations several times:: > > + * > > + * Relaxed CAS update counter.val[0] + 2; counter.val[0] + 1; > > + * Acquired CAS update counter.val[0] + 2; counter.val[0] + 1; > > + * Released CAS update counter.val[0] + 2; counter.val[0] + 1; > > + * Acquired_Released CAS update counter.val[0] + 2; counter.val[= 0] + 1; >=20 Hi Gage, > The array index in "counter.val[0] + 1", is incorrect, I believe. Yes, you are correct. I will fix it. It should be 'counter.val[2] + 1'. >=20 > Just a nitpick, but "Relaxed CAS update" can go last to match the order i= n the > code. Sure. Thank you for your correction. >=20 > >=20 > > +#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64) > > +/* > > + * rte_atomic128_cmp_exchange() should update a 128 bits counter's > > +first 64 > > + * bits by 2 and the second 64 bits by 1 in this test. It should > > +return true > > + * if the compare exchange operation successful. >=20 > "operation successful" -> "operation is successful" Yes. >=20 > > + * This test repeat 128 bits compare and swap operations 10K rounds. > > +In each >=20 > "repeat" -> "repeats" Yes. >=20 > Thanks, > Gage Thanks, Phil