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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5054; H:VE1PR08MB4640.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: f+ucnhrJohlBkl/lPKOqf1G4ABaeW3C2gclv/Suv9wF0rzWGJc68g/O19GS0rrqN8ZVNIg/B0rkUMnbY1sNm8XiuopE+7ydOiPLW9II4otaGtACry8HnQfOKcyms9FPafRO9o2rVLDDk9HNGj1wRDE3gZfgznTuz1Q2wNi4minRbRdnxw8woFs5KWR3QhmRHoGpWlCukfmWACS2oLtfWu13H4RiUuuJ/zpyXZ2nOJwX2zqxAQs5QF1egr2WCas4HQ19hMIm4Otq8PyM8DtzhF99DoNt3hFm0FBaRCklGZZZgz4/I2kyxdETx+sP2+oUJyIcEds5iASKuWgyA1unWpLxDdMfCt6KUB/En7lI6SYGIX2Hj1ckWq0pLXrAOjthqFXB1TcdsZUjsgTGPLIibTW/BHsAJllpE92MaijqYZM0= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 13b61f87-6437-4e40-38af-08d6f8bac3a2 X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 15:43:54.7578 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Phil.Yang@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5054 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Jerin, Thank you for your comments. I will modify these in the next version. Thanks, Phil > -----Original Message----- > From: Jerin Jacob Kollanukkaran > Sent: Monday, June 24, 2019 2:41 PM > To: Phil Yang (Arm Technology China) ; dev@dpdk.org > Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; Honnappa > Nagarahalli ; Gavin Hu (Arm Technology > China) ; nd ; gage.eads@intel.com > Subject: RE: [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchang= e >=20 > > -----Original Message----- > > From: Phil Yang > > Sent: Sunday, June 23, 2019 8:46 AM > > To: dev@dpdk.org > > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran > > ; hemant.agrawal@nxp.com; > > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com; > > gage.eads@intel.com > > Subject: [EXT] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare > > exchange > > > > Add 128-bit atomic compare exchange on aarch64. > > > > Signed-off-by: Phil Yang > > Reviewed-by: Honnappa Nagarahalli > > Tested-by: Honnappa Nagarahalli > > --- > > This patch depends on 'eal/stack: fix 'pointer-sign' warning' > > http://patchwork.dpdk.org/patch/54840/ > > > > + > > +#ifdef __ARM_FEATURE_ATOMICS > > +static inline rte_int128_t > > +__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated, > > +int mo) { >=20 > Better to change to "const int mo". >=20 > > + > > + /* caspX instructions register pair must start from even-numbered > > + * register at operand 1. > > + * So, specify registers for local variables here. > > + */ > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; > > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; > > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; > > + > > + if (mo =3D=3D __ATOMIC_RELAXED) { > > + asm volatile( > > + "casp %[old0], %[old1], %[upd0], %[upd1], > > [%[dst]]" > > + : [old0] "+r" (x0), > > + [old1] "+r" (x1) > > + : [upd0] "r" (x2), > > + [upd1] "r" (x3), > > + [dst] "r" (dst) > > + : "memory"); > > + } else if (mo =3D=3D __ATOMIC_ACQUIRE) { > > + asm volatile( > > + "caspa %[old0], %[old1], %[upd0], %[upd1], > > [%[dst]]" > > + : [old0] "+r" (x0), > > + [old1] "+r" (x1) > > + : [upd0] "r" (x2), > > + [upd1] "r" (x3), > > + [dst] "r" (dst) > > + : "memory"); > > + } else if (mo =3D=3D __ATOMIC_ACQ_REL) { > > + asm volatile( > > + "caspal %[old0], %[old1], %[upd0], %[upd1], > > [%[dst]]" > > + : [old0] "+r" (x0), > > + [old1] "+r" (x1) > > + : [upd0] "r" (x2), > > + [upd1] "r" (x3), > > + [dst] "r" (dst) > > + : "memory"); > > + } else if (mo =3D=3D __ATOMIC_RELEASE) { > > + asm volatile( > > + "caspl %[old0], %[old1], %[upd0], %[upd1], > > [%[dst]]" > > + : [old0] "+r" (x0), > > + [old1] "+r" (x1) > > + : [upd0] "r" (x2), > > + [upd1] "r" (x3), > > + [dst] "r" (dst) > > + : "memory"); >=20 > I think, This duplication code can be avoid with macro and > casp/capsa/casal/caspl as argument. >=20 > > + } else { > > + rte_panic("Invalid memory order\n"); >=20 >=20 > rte_panic should be removed from library. In this case, I think, invalid = mo can > go for strongest barrier. >=20 > > + } > > + > > + old.val[0] =3D x0; > > + old.val[1] =3D x1; > > + > > + return old; > > +} > > +#else > > +static inline rte_int128_t > > +__rte_ldx128(const rte_int128_t *src, int mo) { > > + rte_int128_t ret; > > + if (mo =3D=3D __ATOMIC_ACQUIRE) > > + asm volatile( > > + "ldaxp %0, %1, %2" > > + : "=3D&r" (ret.val[0]), > > + "=3D&r" (ret.val[1]) > > + : "Q" (src->val[0]) > > + : "memory"); > > + else if (mo =3D=3D __ATOMIC_RELAXED) > > + asm volatile( > > + "ldxp %0, %1, %2" > > + : "=3D&r" (ret.val[0]), > > + "=3D&r" (ret.val[1]) > > + : "Q" (src->val[0]) > > + : "memory"); >=20 > Same as above comment. >=20 > > + else > > + rte_panic("Invalid memory order\n"); >=20 > Same as above comment. >=20 > > + > > + return ret; > > +} > > + > > +static inline uint32_t > > +__rte_stx128(rte_int128_t *dst, const rte_int128_t src, int mo) { > > + uint32_t ret; > > + if (mo =3D=3D __ATOMIC_RELEASE) > > + asm volatile( > > + "stlxp %w0, %1, %2, %3" > > + : "=3D&r" (ret) > > + : "r" (src.val[0]), > > + "r" (src.val[1]), > > + "Q" (dst->val[0]) > > + : "memory"); > > + else if (mo =3D=3D __ATOMIC_RELAXED) > > + asm volatile( > > + "stxp %w0, %1, %2, %3" > > + : "=3D&r" (ret) > > + : "r" (src.val[0]), > > + "r" (src.val[1]), > > + "Q" (dst->val[0]) > > + : "memory"); > > + else > > + rte_panic("Invalid memory order\n"); >=20 > Same as above comment. >=20 > > + > > + /* Return 0 on success, 1 on failure */ > > + return ret; > > +} > > +#endif > > + > > +static inline int __rte_experimental > > +rte_atomic128_cmp_exchange(rte_int128_t *dst, > > + rte_int128_t *exp, > > + const rte_int128_t *src, > > + unsigned int weak, > > + int success, > > + int failure) > > +{ > > + // Always do strong CAS >=20 > Remove C++ style code comment.