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Mon, 22 Jul 2019 11:50:38 +0000 Received: from VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::f4e4:378b:49d3:d876]) by VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::f4e4:378b:49d3:d876%5]) with mapi id 15.20.2094.013; Mon, 22 Jul 2019 11:50:37 +0000 From: "Phil Yang (Arm Technology China)" To: "jerinj@marvell.com" , "dev@dpdk.org" CC: "thomas@monjalon.net" , "gage.eads@intel.com" , "hemant.agrawal@nxp.com" , Honnappa Nagarahalli , "Gavin Hu (Arm Technology China)" , nd , nd Thread-Topic: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare exchange Thread-Index: AQHVQHcNR3ozSWPvbkOyQD6LNFihSabWhHRQ Date: Mon, 22 Jul 2019 11:50:37 +0000 Message-ID: References: <1561257671-10316-1-git-send-email-phil.yang@arm.com> <1563785065-12969-1-git-send-email-phil.yang@arm.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: db79792d-e403-48af-b3c1-875436159768.0 x-checkrecipientchecked: true authentication-results: spf=none (sender IP is ) smtp.mailfrom=Phil.Yang@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5104; H:VE1PR08MB4640.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: t6ieA2D996jzboz7fmB+xiYOq4i6VYtLmBRIOxeRScltmNT4eCZbQPZG38Oar7sMfy6Zpwp305JBopFZCvmnRfZyn/Yv1OKdw6r8vBvLo+c9hz7B4YLOqTrDMM7TtcMGlwXk03Q9OqNbhUAMvaxSPIMSBZxlesyGJOgNcKgU8UnGVX8gK6gGp1LakZbwP16G/6tfYRKANOyVUPm4oY5jANfqENTcqkHLqv+bTNgkVOY6vU/HD0NIN0e1TkQ3tjDtgO5z6DUY+QcNsQjzfVj5o3oxiqGFkopdvWT02z7rfdmmZerZsXF+9BGQP0EdSW2eV6VzNpZeE+j8Js//N+G87c6/nyYtkndpITrPn66K2SXbA2VHNY7ww2whtGknMk0uzo78wsS5ArugSnLjTcZb/mMMVVh4h8XUqvqLivSmxEE= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58dfcb19-3c56-4ced-9e11-08d70e9ad05b X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jul 2019 11:50:37.7353 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Phil.Yang@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5104 Subject: Re: [dpdk-dev] [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob Kollanukkaran > Sent: Monday, July 22, 2019 6:20 PM > To: Phil Yang (Arm Technology China) ; dev@dpdk.org > Cc: thomas@monjalon.net; gage.eads@intel.com; > hemant.agrawal@nxp.com; Honnappa Nagarahalli > ; Gavin Hu (Arm Technology China) > ; nd > Subject: RE: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 > > -----Original Message----- > > From: Phil Yang > > Sent: Monday, July 22, 2019 2:14 PM > > To: dev@dpdk.org > > Cc: thomas@monjalon.net; Jerin Jacob Kollanukkaran > ; > > gage.eads@intel.com; hemant.agrawal@nxp.com; > > Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com > > Subject: [EXT] [PATCH v4 1/3] eal/arm64: add 128-bit atomic compare > exchange > > Add 128-bit atomic compare exchange on aarch64. > > > > Suggested-by: Jerin Jacob > > Signed-off-by: Phil Yang > > Tested-by: Honnappa Nagarahalli > > Reviewed-by: Honnappa Nagarahalli > > + > > +# > > +# Compile ARM LSE ATOMIC instructions statically # >=20 > There is NO value for the keyword "statically" here. Right? Agree. Will remove it. >=20 > > +CONFIG_RTE_ARM_FEATURE_ATOMICS=3Dn >=20 >=20 > > diff --git a/config/defconfig_arm64-thunderx2-linuxapp-gcc > > b/config/defconfig_arm64-thunderx2-linuxapp-gcc > > index cc5c64b..17b6dec 100644 > > --- a/config/defconfig_arm64-thunderx2-linuxapp-gcc > > +++ b/config/defconfig_arm64-thunderx2-linuxapp-gcc > > @@ -6,6 +6,7 @@ > > > > CONFIG_RTE_MACHINE=3D"thunderx2" > > > > +CONFIG_RTE_ARM_FEATURE_ATOMICS=3Dy >=20 >=20 > Add for octeontx2 as well. OK. Will add it in v5. >=20 > > CONFIG_RTE_CACHE_LINE_SIZE=3D64 > > CONFIG_RTE_MAX_NUMA_NODES=3D2 > > CONFIG_RTE_MAX_LCORE=3D256 >=20 >=20 > > +rte_atomic128_cmp_exchange(rte_int128_t *dst, > > + rte_int128_t *exp, > > + const rte_int128_t *src, > > + unsigned int weak, > > + int success, > > + int failure) > > +{ > > + /* Always do strong CAS */ > > + RTE_SET_USED(weak); > > + /* Ignore memory ordering for failure, memory order for > > + * success must be stronger or equal > > + */ > > + RTE_SET_USED(failure); > > + /* Find invalid memory order */ > > + RTE_ASSERT(success =3D=3D __ATOMIC_RELAXED > > + || success =3D=3D __ATOMIC_ACQUIRE > > + || success =3D=3D __ATOMIC_RELEASE > > + || success =3D=3D __ATOMIC_ACQ_REL > > + || success =3D=3D __ATOMIC_SEQ_CST); > > + > > +#ifdef __ARM_FEATURE_ATOMICS >=20 > Shouldn't it be #if defined(__ARM_FEATURE_ATOMICS) || > defined(RTE_ARM_FEATURE_ATOMICS) ? Yes. That was a mistake. Will update in the version 5. Thanks. Thanks, Phil Yang