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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4783; H:VE1PR08MB4640.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Ab22teEoQzOXRVfqjLCaE0lBr28emkly+jkFApaXYbrrrNhGjMMF/oHAKPYhAxPV8RYSxm+gMWOa0fKZ1JHh1LjuuVhkwkc3kcemwFFDtjLdQlZy4cwVpB4Bobo39XQLugrV25LVdL1IkvPVO6fVJerZBFIRVlyW59ywykatNdTbOoPIgi4V9BASgn6IfXqP3txXRgCBlpHUqGgo7wAoIwh5ENqPBF61lrLUDMZ6CXIEjWpuoB5DZIqyhx323kVb5Y8Id4v4frUPBkMdaHupD2n/cw+7tREKGSZeR/DM+mr9VMx7rmRgqoaW4mDjo7UJtbdZiDDOifi7rm/E8rWSO96W9eh0Lckr0d5PcwVEDjv0afWbKqPacTS7dmeHFLgitb4PxiBe4b2n0p20rGWwGGmx+ua+NaiUxWs3V04wgcw= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 332e9b57-d124-4cbe-b1c6-08d6fa1e902e X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Jun 2019 10:10:49.3586 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Phil.Yang@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4783 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Jerin Jacob Kollanukkaran > Sent: Tuesday, June 25, 2019 2:16 PM > To: Honnappa Nagarahalli ; > thomas@monjalon.net; Phil Yang (Arm Technology China) > > Cc: dev@dpdk.org; hemant.agrawal@nxp.com; Gavin Hu (Arm Technology > China) ; nd ; gage.eads@intel.com; nd > > Subject: RE: [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchang= e >=20 > > -----Original Message----- > > From: Honnappa Nagarahalli > > Sent: Monday, June 24, 2019 11:11 PM > > To: thomas@monjalon.net; Phil Yang (Arm Technology China) > > > > Cc: Jerin Jacob Kollanukkaran ; dev@dpdk.org; > > hemant.agrawal@nxp.com; Gavin Hu (Arm Technology China) > > ; Honnappa Nagarahalli > > ; nd ; > gage.eads@intel.com; > > nd > > Subject: [EXT] RE: [PATCH v2 1/3] eal/arm64: add 128-bit atomic > > compare exchange > > > > > > 24/06/2019 18:12, Honnappa Nagarahalli: > > > > > > > + } else { > > > > > > > + rte_panic("Invalid memory order\n"); > > > > > > > > > > > > > > > > > > rte_panic should be removed from library. In this case, I > > > > > > think, invalid mo can go for strongest barrier. > > > > > > > > It is added here to capture programming errors. > > > > Memory order can be passed during compilation or during run time. > > > > 'rte_panic' supports both of these. > > > > Adding code with strongest memory order will mask the programming > error. > > > > > > An error must return a specific code from the function. > > > rte_panic is really forbidden in libraries. > > > We are in the process of removing all of them. > > Thank you for clarifying. > > In this particular use case, the API is similar to > '__atomic_compare_exchange' > > built-in. Users would expect similar behavior. If we are differing > > from the standard behavior, we should document it in the API definition= . >=20 > IMO, We should not differ from the standard behavior(return type) of > atomic_compare_exchange. > And we should not have rte_panic in library. IMO, Best option would be > 1) If mo is compile time constant then check with RTE_BUILD_ON for static > assert to find invalid mo I think we need to add static assert in the rte_atomic128_cmp_exchange to c= heck invalid mo, rather than put it in these 3 internal functions. Because the mo parameter is passed from the rte_atomic128_cmp_exchange. > 2) if mo is runtime value and it is invalid then move to strongest memory > order to make functionally correct When the mo is runtime value, the compiler will always use the strongest me= mory order to predict atomic operations. Please check the URL (https://gcc.= godbolt.org/z/GDx6Ob) for the details.=20 So I think, in these 3 internal functions (__rte_ldx128, __rte_strx128, __r= te_casp), it is sufficient to just follow this rule. Thanks, Phil Yang >=20 >=20 > > > > > > > >