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Fri, 17 Jul 2020 04:44:47 +0000 Received: from VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::c2e:9ccb:a690:6863]) by VE1PR08MB4640.eurprd08.prod.outlook.com ([fe80::c2e:9ccb:a690:6863%6]) with mapi id 15.20.3174.026; Fri, 17 Jul 2020 04:44:47 +0000 From: Phil Yang To: Honnappa Nagarahalli , "thomas@monjalon.net" , "john.mcnamara@intel.com" , "drc@linux.vnet.ibm.com" , "dev@dpdk.org" CC: "david.marchand@redhat.com" , "jerinj@marvell.com" , "konstantin.ananyev@intel.com" , Ola Liljedahl , "bruce.richardson@intel.com" , Ruifeng Wang , nd , Marko Kovacevic , nd , nd Thread-Topic: [PATCH v8 1/3] doc: add optimizations using C11 atomic built-ins Thread-Index: AQHWW54cadhRlhrT30eOvFY1Vy3/0qkLMl1Q Date: Fri, 17 Jul 2020 04:44:47 +0000 Message-ID: References: <1594621423-14796-1-git-send-email-phil.yang@arm.com> <1594875225-5850-1-git-send-email-phil.yang@arm.com> <1594875225-5850-2-git-send-email-phil.yang@arm.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 2a85bf6c-cf06-4605-8f36-0e770cbae67a.0 x-checkrecipientchecked: true Authentication-Results-Original: arm.com; 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X-Microsoft-Antispam-Message-Info: o2GDGQscohycAhCAL3/5QNT4uVkz/ScnmA3+YbotictPtfTg9C+JQxs/uCt96UQRuW+/NCPaKJbKBPdckSgh2ecs2KzRiCpJAYTq23Sk2IG5PAC2WEYpIrsewWX+nHk5VRdPlGa5SnWOju134QcDF6bQyS+GQJWtOG7fTT4fw3ZnrMR0cnykF9CQzWjgbTp83sLYePYOVSw6FLNUIyxXwh25A30caHrGhkz40yOXKIl+trXNnzbItP+o5jzWmwGJVPKkB7DziLYAZ/0ClOoEmvd7yz3M0d0MVLA0VA7Ea5JLI2UMPcJ9YcvlNp5IkVkl1kJTwngtwNVBLczes/una1BR+fN2XfWx06a1AMENc9M0nWWDmszma36liCwNv6AbRsBtLcKcXUAJXvfAxMSoRQ== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2020 04:44:54.0624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ae56512-5b05-415e-5471-08d82a0c2624 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2260 Subject: Re: [dpdk-dev] [PATCH v8 1/3] doc: add optimizations using C11 atomic built-ins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Honnappa Nagarahalli writes: >=20 > > Subject: [PATCH v8 1/3] doc: add optimizations using C11 atomic built-i= ns > > > > Add information about possible optimizations using C11 atomic built-ins= . > > > > Signed-off-by: Phil Yang > > Signed-off-by: Honnappa Nagarahalli >=20 > Thanks for the changes, they look good now. >=20 > David wanted to change 'built-ins' to 'builtins', otherwise > Reviewed-by: Honnappa Nagarahalli Will do in the next version. Thanks. >=20 > > --- > > doc/guides/prog_guide/writing_efficient_code.rst | 59 > > +++++++++++++++++++++++- > > 1 file changed, 58 insertions(+), 1 deletion(-) > > > > diff --git a/doc/guides/prog_guide/writing_efficient_code.rst > > b/doc/guides/prog_guide/writing_efficient_code.rst > > index 849f63e..53a1ca1 100644 > > --- a/doc/guides/prog_guide/writing_efficient_code.rst > > +++ b/doc/guides/prog_guide/writing_efficient_code.rst > > @@ -167,7 +167,13 @@ but with the added cost of lower throughput. > > Locks and Atomic Operations > > --------------------------- > > > > -Atomic operations imply a lock prefix before the instruction, > > +This section describes some key considerations when using locks and > > +atomic operations in the DPDK environment. > > + > > +Locks > > +~~~~~ > > + > > +On x86, atomic operations imply a lock prefix before the instruction, > > causing the processor's LOCK# signal to be asserted during execution o= f > the > > following instruction. > > This has a big impact on performance in a multicore environment. > > > > @@ -176,6 +182,57 @@ It can often be replaced by other solutions like p= er- > > lcore variables. > > Also, some locking techniques are more efficient than others. > > For instance, the Read-Copy-Update (RCU) algorithm can frequently > replace > > simple rwlocks. > > > > +Atomic Operations: Use C11 Atomic Built-ins > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +DPDK generic rte_atomic operations are implemented by __sync built-ins= . > > +These __sync built-ins result in full barriers on aarch64, which are > > +unnecessary in many use cases. They can be replaced by __atomic > > +built-ins that conform to the C11 memory model and provide finer > memory > > order control. > > + > > +So replacing the rte_atomic operations with __atomic built-ins might > > +improve performance for aarch64 machines. > > + > > +Some typical optimization cases are listed below: > > + > > +Atomicity > > +^^^^^^^^^ > > + > > +Some use cases require atomicity alone, the ordering of the memory > > +operations does not matter. For example, the packet statistics counter= s > > +need to be incremented atomically but do not need any particular > memory > > ordering. > > +So, RELAXED memory ordering is sufficient. > > + > > +One-way Barrier > > +^^^^^^^^^^^^^^^ > > + > > +Some use cases allow for memory reordering in one way while requiring > > +memory ordering in the other direction. > > + > > +For example, the memory operations before the spinlock lock are allowe= d > > +to move to the critical section, but the memory operations in the > > +critical section are not allowed to move above the lock. In this case, > > +the full memory barrier in the compare-and-swap operation can be > replaced > > with ACQUIRE memory order. > > +On the other hand, the memory operations after the spinlock unlock are > > +allowed to move to the critical section, but the memory operations in > > +the critical section are not allowed to move below the unlock. So the > > +full barrier in the store operation can use RELEASE memory order. > > + > > +Reader-Writer Concurrency > > +^^^^^^^^^^^^^^^^^^^^^^^^^ > > + > > +Lock-free reader-writer concurrency is one of the common use cases in > DPDK. > > + > > +The payload or the data that the writer wants to communicate to the > > +reader, can be written with RELAXED memory order. However, the guard > > +variable should be written with RELEASE memory order. This ensures tha= t > > +the store to guard variable is observable only after the store to payl= oad is > > observable. > > + > > +Correspondingly, on the reader side, the guard variable should be read > > +with ACQUIRE memory order. The payload or the data the writer > > +communicated, can be read with RELAXED memory order. This ensures > that, > > +if the store to guard variable is observable, the store to payload is = also > > observable. > > + > > Coding Considerations > > --------------------- > > > > -- > > 2.7.4