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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4943; H:VE1PR08MB4640.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: E6vlO+uqpM/Lz0yZhJ8NVet/g2axsLBca5rLpt+kAwNzSYH6RvjKgovxr8iCHYf4B6V3rXts1ciDoea5F46vEKAiucqJoW3oaw6K6kIoAIJ+cRhcphTBdSFjlVImSM5tGI6oCONTjsmXhTlzhCx14TAjpUB+z1g1pGgPyQWhDT6AmaqTMVGwazfMkMcmoESOfCsECMUa9v+ww/wI23ZcRPolNEax9yUwE7h+ntmvqnlmKj4DMEiSvr932SMDzn9t2Zb5HDegxGJbECI81gxqyVmTJE80hrUXfoIqQ99q+ZW+u8tYT1su4bqxjOTGmOP26RA4suu9t5Q0P6JibRE+iPcsBGXhxOLoogS9iHDVCTRve/s/qb0Km3keRuaykOs3bOMxEG8q9K34s8S1VG/OpoO6EK4CPC0pYlU0zRJu3Yo= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7ededea3-4ee5-48a0-54f5-08d7044fab96 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2019 09:27:32.2908 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Phil.Yang@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4943 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Pavan Nikhilesh Bhagavatula > Sent: Friday, July 5, 2019 12:37 PM > To: Honnappa Nagarahalli ; > jerinj@marvell.com; Phil Yang (Arm Technology China) > ; dev@dpdk.org > Cc: thomas@monjalon.net; hemant.agrawal@nxp.com; Gavin Hu (Arm > Technology China) ; nd ; > gage.eads@intel.com; nd > Subject: RE: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > exchange >=20 >=20 > >> > > +#ifdef __ARM_FEATURE_ATOMICS > >> > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) > >> \ > >> > > +static inline rte_int128_t = \ > >> > > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > >> > > + rte_int128_t updated) = \ > >> > > +{ = \ > >> > > + /* caspX instructions register pair must start from even- > >numbered > >> > > + * register at operand 1. > >> > > + * So, specify registers for local variables here. > >> > > + */ = \ > >> > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > \ > >> > > >> > I understand CASP limitation on register has to be even and odd. > >> > Is there anyway to remove explicit x0 register allocation and choose > >> > compiler to decide the register. Some reason with optimize(03) gcc > >> > makes correctly but not clang. > >> > > >> > Hardcoding to specific register makes compiler to not optimize the > >> > stuff, especially if it is inline function. > >> > >> It look like the limitation fixed recently in gcc. > >> https://patches.linaro.org/patch/147991/ > >> > >> Not sure about old gcc and clang. ARM compiler experts may know > >the exact > >> status > >> > >We could use syntax as follows, an example is in [1] > >static inline rte_int128_t > >__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated, > >int mo) > >{ > > __asm__ volatile("caspl %0, %H0, %1, %H1, [%2]" > > : "+r" (old) > > : "r" (updated), "r" (dst) > > : "memory"); > > return old; > >} >=20 > We have used this format for mempool/octeontx2 but clang wasn't too > happy. >=20 > dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:151:15: error: > value size does not match register size specified by the constraint and > modifier [-Werror,-Wasm-operand-widths] > [t0] "=3D&r" (t0), [t1] "=3D&r" (t1), [t2] "=3D&r" (t2), > ^ > dpdk/drivers/mempool/octeontx2/otx2_mempool_ops.c:82:9: note: use > constraint modifier "w" > "casp %[t0], %H[t0], %[wdata], %H[wdata], [%[loc]]\n" >=20 > Had to change it to hand coded asm >=20 > http://patches.dpdk.org/patch/56110/ Hi Jerin, The update from the compiler team is 'the LSE CASP fix has not been backpor= ted to older GCC branches'. So, currently, this seems the only approach works for all versions of GCC a= nd Clang.=20 I think we can add another optimization patch for this once all the compile= rs were ready.=20 Thanks, Phil >=20 > > > >[1] https://godbolt.org/z/EUJnuG