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Tue, 29 Oct 2019 05:47:25 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::8c82:8d9c:c78d:22a6]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::8c82:8d9c:c78d:22a6%7]) with mapi id 15.20.2387.027; Tue, 29 Oct 2019 05:47:25 +0000 From: Honnappa Nagarahalli To: "thomas@monjalon.net" CC: Jerin Jacob , Ola Liljedahl , "Gavin Hu (Arm Technology China)" , "dev@dpdk.org" , "pbhagavatula@marvell.com" , nd , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , "bruce.richardson@intel.com" , Honnappa Nagarahalli , nd Thread-Topic: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration Thread-Index: AQHVhTjdjUGPgoqrmUGLW39o/DcA+adfzawQgAAxqICAByYYEIAH6WS/gABkJaCAAFhAgIABWWsQ Date: Tue, 29 Oct 2019 05:47:25 +0000 Message-ID: References: <1564615940-13183-1-git-send-email-gavin.hu@arm.com> <2227745.9fKeDGhzLh@xps> <42494108.RkbLAJnAIz@xps> In-Reply-To: <42494108.RkbLAJnAIz@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: f9b7f65b-3c3f-47d2-a4aa-c6c6e5903cbd.0 x-checkrecipientchecked: true Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4491 Subject: Re: [dpdk-dev] [PATCH v2 2/3] config: add arm neoverse N1 SDP configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > 28/10/2019 04:24, Honnappa Nagarahalli: > > > 23/10/2019 07:03, Jerin Jacob: > > > > On Wed, Oct 23, 2019 at 2:37 AM Honnappa Nagarahalli > > > > wrote: > > > > > > > > On Thu, 2019-08-01 at 07:48 +0800, Gavin Hu wrote: > > > > > > > > > Arm N1 SDP is an infrastructure segment development > > > > > > > > > platform based on armv8.2-a Neoverse N1 CPU. For more > > > > > > > > > information, refer > > > to: > > > > > > > > > https://community.arm.com/developer/tools-software/oss-p > > > > > > > > > latf > > > > > > > > > orms/w > > > > > > > > > / > > > > > > > > > docs/440/neoverse-n1-sdp > > > > > > > > > > > > > > > > > > Signed-off-by: Gavin Hu > > > > > > > > > Reviewed-by: Honnappa Nagarahalli > > > > > > > > > > > > > > > > > > Reviewed-by: Steve Capper > > > > > > > > > --- > > > > > > > > > +CONFIG_RTE_MACHINE=3D"neoversen1" > > > > > > > > This should probably be "n1sdp" as this is the name of the > > > > > > > > platform that matches the below configuration. > > > > > > > A clear definition of RTE_MACHINE is required. Jerin? > > > > > > > > > > > > I think, In the existing scheme of things, RTE_MACHINE > > > > > > defines, where to take the MACHINE_CFLAGS > > > > > > mk/machine/xxxx/rte.vars.mk > > > > > Ok, thank you > > > > > > > > > > > > > > > > > Considering the fact that there will be a lot of reusable > > > > > > IPs(for > > > > > > CPU) from ARM for armv8, I think, it would make sense to > > > > > > introduce RTE_MICRO_ARCH to avoid a lot of code duplications > > > > > > and > > > confusion. > > > > > > > > > > > > RTE_ARCH example: "x86" or "arm64" I see that there are already RTE_ARCH_X86, RTE_ARCH_ARM, RTE_ARCH_ARM64, RT= E_ARCH_PPC_64 etc. I believe they should be sufficient. > > > > > > RTE_MICRO_ARCH example: "a72" or "thunderx3" - de= fines > > > > > > mcpu and armv8 verion arch etc Are you suggesting this just for Arm platforms? My understanding is your intention was to clean up the config/arm/meson.bui= ld file. > > > > > > RTE_MACHINE example: "bluefield" or "thun= derx3" > > > > > > - defines, number of cores, NUMA or not? etc > > > > > Looking at mk/machine/ directory, looks like RTE_MACHINE seems > > > > > to be > > > defining micro-architecture for Intel. For ex: hsw, nhm, wsm. I see > > > the same for Arm as well. > > > > > Are you suggesting that we use RTE_MICRO_ARCH to pick mk/micro- > > > arch/xxxx/rte.vars.mk? and RTE_MACHINE would pick > > > mk/machine/xxxx/rte.vars.mk, but contain NUMA, #of cores etc? > > > > > > > > Yes for Make build. I think, it is deprecated soon, so we need a > > > > similar solution for meson. > > > > > > Yes I would prefer we clean the mess in Meson, instead of talking > > > about the makefile system. > > > And honestly, N1 is not needed in the legacy makefile system. > > Unfortunately, most of the guys I talk to are still on makefile. >=20 > You need to help them to switch. > Adding new targets in meson-only can be a good motivation :) >=20 > > When is makefile system getting removed? >=20 > It must be clearly decided and announced. > The previous techboard discussions were about making makefile hardly > usable during 2020, i.e. very soon. >=20 > > > So focusing on config/arm/meson.build, I think RTE_MACHINE is > > > defined only for API compatibility with makefile. > > > However, I doubt this value is used by any application. > > > I think we can try to remove RTE_MACHINE from meson builds in DPDK > > > 19.11, or use RTE_MACHINE as micro-arch (my preference). > > 'MACHINE' means different things to different people, which is the root > cause of this discussion. > > 'MICRO-ARCH' has a very clear meaning. Do you see any problem going > with MICRO-ARCH instead? >=20 > Some applications may use RTE_MACHINE for this purpose. > It is part of the API since the befinning of DPDK. > I don't see a real motivation to break this API now. The suggestions are not clear to me. The original suggestion was to introdu= ce RTE_MICRO_ARCH and contain all the micro-architecture related compiler f= lags in that. Now, the suggestion is to use RTE_MACHINE to contain micro-architecture rel= ated compiler flags. Will it contain NUMA, number of cores as well (as sugg= ested earlier)? If yes, I do not see it changing anything. I am not a meson expert. However, I looked at various meson.build files. I = have few questions/concerns. 1) Are these suggestions are for all the platforms? IMO, these need to be t= he same across all the architectures. 2) I am looking at config/meson.build. Here RTE_MACHINE is defined to indic= ate Architecture for Arm (armv7-a, aarchxx) and micro-architecture for x86 = (corei7?). Is the understanding correct? IMO, this should this have a commo= n meaning across all the platforms? 3) If the changes are for all the platforms, is the risk high for 19.11 rel= ease? 4) The N1 config patch as such conforms to the current conventions. What is= being asked here is an enhancement, is the understanding correct? >=20