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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4613 Subject: Re: [dpdk-dev] [PATCH v7 02/17] lib/ring: apis to support configurable element size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > > + > > > > > +static __rte_always_inline void enqueue_elems_128(struct > > > > > +rte_ring *r, uint32_t prod_head, const void *obj_table, > > > > > +uint32_t n) { unsigned int i; const uint32_t size =3D r->size; > > > > > +uint32_t idx =3D prod_head & r->mask; __uint128_t *ring =3D > > > > > +(__uint128_t *)&r[1]; const __uint128_t *obj =3D (const > > > > > +__uint128_t *)obj_table; if (likely(idx + n < size)) { for (i = =3D > > > > > +0; i < (n & ~0x1); i +=3D 2, idx +=3D 2) { ring[idx] =3D obj[i]; > > > > > +ring[idx + 1] =3D obj[i + 1]; > > > > > > > > > > > > AFAIK, that implies 16B aligned obj_table... > > > > Would it always be the case? > > > I am not sure from the compiler perspective. > > > At least on Arm architecture, unaligned access (address that is > > > accessed is not aligned to the size of the data element being > > > accessed) will result in faults or require additional cycles. So, ali= gning on > 16B should be fine. > > Further, I would be changing this to use 'rte_int128_t' as '__uint128_t= ' is > not defined on 32b systems. >=20 > What I am trying to say: with this code we imply new requirement for elem= s The only existing use case in DPDK for 16B is the event ring. The event rin= g already does similar kind of copy (using 'struct rte_event'). So, there i= s no change in expectations for event ring. For future code, I think this expectation should be fine since it allows fo= r optimal code. > in the ring: when sizeof(elem)=3D=3D16 it's alignment also has to be at l= east 16. > Which from my perspective is not ideal. Any reasoning? > Note that for elem sizes > 16 (24, 32), there is no such constraint. The rest of them need to be aligned on 4B boundary. However, this should no= t affect the existing code. The code for 8B and 16B is kept as is to ensure the performance is not affe= cted for the existing code. >=20 > > > > > > > > > > > > > > +} > > > > > +switch (n & 0x1) { > > > > > +case 1: > > > > > +ring[idx++] =3D obj[i++]; > > > > > +} > > > > > +} else { > > > > > +for (i =3D 0; idx < size; i++, idx++) ring[idx] =3D obj[i]; > > > > > +/* Start at the beginning */ > > > > > +for (idx =3D 0; i < n; i++, idx++) ring[idx] =3D obj[i]; } } > > > > > + > > > > > +/* the actual enqueue of elements on the ring. > > > > > + * Placed here since identical code needed in both > > > > > + * single and multi producer enqueue functions. > > > > > + */ > > > > > +static __rte_always_inline void enqueue_elems(struct rte_ring > > > > > +*r, uint32_t prod_head, const void > > > > *obj_table, > > > > > +uint32_t esize, uint32_t num) > > > > > +{ > > > > > +uint32_t idx, nr_idx, nr_num; > > > > > + > > > > > +/* 8B and 16B copies implemented individually to retain > > > > > + * the current performance. > > > > > + */ > > > > > +if (esize =3D=3D 8) > > > > > +enqueue_elems_64(r, prod_head, obj_table, num); else if (esize > > > > > +=3D=3D > > > > > +16) enqueue_elems_128(r, prod_head, obj_table, num); else { > > > > > +/* Normalize to uint32_t */ > > > > > +uint32_t scale =3D esize / sizeof(uint32_t); nr_num =3D num * > > > > > +scale; idx =3D prod_head & r->mask; nr_idx =3D idx * scale; > > > > > +enqueue_elems_32(r, nr_idx, obj_table, nr_num); } } > > > > > +