From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <Honnappa.Nagarahalli@arm.com> Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80085.outbound.protection.outlook.com [40.107.8.85]) by dpdk.org (Postfix) with ESMTP id ED0185B26 for <dev@dpdk.org>; Mon, 15 Apr 2019 06:35:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bwHeDpcrAaG2SV4JHmyo/vPCQZSYwEES8ZV7DGvMY0Q=; b=Utn3dTCEbCpuwEGF/LaanVO/2EozNwQknvzO8qmiHcaAhcTqEwc5DCC/vJ72UuKf6Z4Ra6ndum1/FBWuvBjpKNY/di6Y5a2b1MLrA1chziv53j5EVNeGTrFR/YGsOWID71T5w9OzuJU4bt1WAq1iAhmjEAVA4psnKZoul3IUjKg= Received: from VE1PR08MB5149.eurprd08.prod.outlook.com (20.179.30.152) by VE1PR08MB4861.eurprd08.prod.outlook.com (10.255.113.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Mon, 15 Apr 2019 04:35:39 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::e0ae:ecad:ec5:8177]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::e0ae:ecad:ec5:8177%2]) with mapi id 15.20.1792.018; Mon, 15 Apr 2019 04:35:39 +0000 From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com> To: "jerinj@marvell.com" <jerinj@marvell.com>, "yskoh@mellanox.com" <yskoh@mellanox.com>, "bruce.richardson@intel.com" <bruce.richardson@intel.com>, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>, "shahafs@mellanox.com" <shahafs@mellanox.com> CC: "dev@dpdk.org" <dev@dpdk.org>, "thomas@monjalon.net" <thomas@monjalon.net>, "Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>, Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, nd <nd@arm.com>, nd <nd@arm.com> Thread-Topic: [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 Thread-Index: AQHU8Yb4imTG5knQF0WAOuqpUrB6m6Y5pVqAgAL4iJA= Date: Mon, 15 Apr 2019 04:35:38 +0000 Message-ID: <VE1PR08MB514985341EAE0821BBF273F8982B0@VE1PR08MB5149.eurprd08.prod.outlook.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-3-yskoh@mellanox.com> <BYAPR18MB24248C9353FC4990051E7DE8C8290@BYAPR18MB2424.namprd18.prod.outlook.com> In-Reply-To: <BYAPR18MB24248C9353FC4990051E7DE8C8290@BYAPR18MB2424.namprd18.prod.outlook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4861; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wsMzu559yjdORleaaOYy4Y2xnJjHhP/dnwSi9Q42B2knJ6/7WGxg+RJYk3Ymcu5MHhPk/PTeziwnAay7f78bcmhJ5LsCtqCfxLxHNZjtNcUyUVjusGKZUg1VAvqFABkWA8lJZJTXqD39lQWU5n0VNjojHQaXhwomHyLZLrnu2WXGwiqTkTBgXXQk7IdZpQe1fNtNISUckzTc+amiJIznBzJGLo1gEUpWtpbHASPVIejHNlE4ooBTPgIz5rRT38VNGUPsF55rn8B+dERUhfWo0LGosiR3QlbEe+Rze7eSG1unRRfgjoWlUX4KTXlRI8L/+qjgNwC1nf5GLnF5MKfnQSBFhHw2/asmRWQMee15jRVpPf8EEAPh3mtXKk/d25a3WRqEAfeBKiZTED4gvWvjPhe43COh/qRgvaC1Qu47Sjo= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86d27d54-c1ff-46e3-b929-08d6c15bcfc6 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 04:35:39.0014 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4861 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Mon, 15 Apr 2019 04:35:42 -0000 > > > > ---------------------------------------------------------------------- > > Per the email discussion [1], the default cache line size of armv8 > > cortex-a72 is changed to 64 bytes. >=20 > IMO, In git commit you remove the reference to specific discussion and > Update the reason correctly. >=20 >=20 > > > > [1] https://mails.dpdk.org/archives/dev/2019-January/123218.html > > > > Signed-off-by: Yongseok Koh <yskoh@mellanox.com> > > --- > > config/arm/meson.build | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > e00b894523..73c581948c 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ > > ['RTE_MAX_LCORE', 16], > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra > =3D [] > > +flags_cortex_a72_extra =3D [ > > + ['RTE_CACHE_LINE_SIZE', 64]] > > flags_thunderx_extra =3D [ Which tree does this patch apply to? I do not see the above line in master. > > ['RTE_MACHINE', '"thunderx"'], > > ['RTE_USE_C11_MEM_MODEL', false]] > > @@ -73,7 +75,7 @@ machine_args_generic =3D [ > > ['0xd03', ['-mcpu=3Dcortex-a53']], > > ['0xd04', ['-mcpu=3Dcortex-a35']], > > ['0xd07', ['-mcpu=3Dcortex-a57']], > > - ['0xd08', ['-mcpu=3Dcortex-a72']], > > + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], > > ['0xd09', ['-mcpu=3Dcortex-a73']], > > ['0xd0a', ['-mcpu=3Dcortex-a75']]] >=20 > I think, flags_cortex_a72_extra() can be changed to > flags_vendor_arm_extra or something similar And update the following > CPUs also not just cortex-a72. >=20 Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All the lis= ted Arm cores are 64B cache line size. > ['0xd03', ['-mcpu=3Dcortex-a53']], > ['0xd04', ['-mcpu=3Dcortex-a35']], > ['0xd05', ['-mcpu=3Dcortex-a55']], > ['0xd07', ['-mcpu=3Dcortex-a57']], > ['0xd08', ['-mcpu=3Dcortex-a72']], > ['0xd09', ['-mcpu=3Dcortex-a73']], > ['0xd0a', ['-mcpu=3Dcortex-a75']], > ['0xd0b', ['-mcpu=3Dcortex-a76']], >=20 >=20 > > > > -- > > 2.21.0.196.g041f5ea From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 1BF64A00E6 for <public@inbox.dpdk.org>; Mon, 15 Apr 2019 06:35:45 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 666A35B2C; Mon, 15 Apr 2019 06:35:43 +0200 (CEST) Received: from EUR04-VI1-obe.outbound.protection.outlook.com (mail-eopbgr80085.outbound.protection.outlook.com [40.107.8.85]) by dpdk.org (Postfix) with ESMTP id ED0185B26 for <dev@dpdk.org>; Mon, 15 Apr 2019 06:35:41 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bwHeDpcrAaG2SV4JHmyo/vPCQZSYwEES8ZV7DGvMY0Q=; b=Utn3dTCEbCpuwEGF/LaanVO/2EozNwQknvzO8qmiHcaAhcTqEwc5DCC/vJ72UuKf6Z4Ra6ndum1/FBWuvBjpKNY/di6Y5a2b1MLrA1chziv53j5EVNeGTrFR/YGsOWID71T5w9OzuJU4bt1WAq1iAhmjEAVA4psnKZoul3IUjKg= Received: from VE1PR08MB5149.eurprd08.prod.outlook.com (20.179.30.152) by VE1PR08MB4861.eurprd08.prod.outlook.com (10.255.113.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1792.15; Mon, 15 Apr 2019 04:35:39 +0000 Received: from VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::e0ae:ecad:ec5:8177]) by VE1PR08MB5149.eurprd08.prod.outlook.com ([fe80::e0ae:ecad:ec5:8177%2]) with mapi id 15.20.1792.018; Mon, 15 Apr 2019 04:35:39 +0000 From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com> To: "jerinj@marvell.com" <jerinj@marvell.com>, "yskoh@mellanox.com" <yskoh@mellanox.com>, "bruce.richardson@intel.com" <bruce.richardson@intel.com>, Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>, "shahafs@mellanox.com" <shahafs@mellanox.com> CC: "dev@dpdk.org" <dev@dpdk.org>, "thomas@monjalon.net" <thomas@monjalon.net>, "Gavin Hu (Arm Technology China)" <Gavin.Hu@arm.com>, Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, nd <nd@arm.com>, nd <nd@arm.com> Thread-Topic: [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 Thread-Index: AQHU8Yb4imTG5knQF0WAOuqpUrB6m6Y5pVqAgAL4iJA= Date: Mon, 15 Apr 2019 04:35:38 +0000 Message-ID: <VE1PR08MB514985341EAE0821BBF273F8982B0@VE1PR08MB5149.eurprd08.prod.outlook.com> References: <20190412232451.30197-1-yskoh@mellanox.com> <20190412232451.30197-3-yskoh@mellanox.com> <BYAPR18MB24248C9353FC4990051E7DE8C8290@BYAPR18MB2424.namprd18.prod.outlook.com> In-Reply-To: <BYAPR18MB24248C9353FC4990051E7DE8C8290@BYAPR18MB2424.namprd18.prod.outlook.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Honnappa.Nagarahalli@arm.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4861; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wsMzu559yjdORleaaOYy4Y2xnJjHhP/dnwSi9Q42B2knJ6/7WGxg+RJYk3Ymcu5MHhPk/PTeziwnAay7f78bcmhJ5LsCtqCfxLxHNZjtNcUyUVjusGKZUg1VAvqFABkWA8lJZJTXqD39lQWU5n0VNjojHQaXhwomHyLZLrnu2WXGwiqTkTBgXXQk7IdZpQe1fNtNISUckzTc+amiJIznBzJGLo1gEUpWtpbHASPVIejHNlE4ooBTPgIz5rRT38VNGUPsF55rn8B+dERUhfWo0LGosiR3QlbEe+Rze7eSG1unRRfgjoWlUX4KTXlRI8L/+qjgNwC1nf5GLnF5MKfnQSBFhHw2/asmRWQMee15jRVpPf8EEAPh3mtXKk/d25a3WRqEAfeBKiZTED4gvWvjPhe43COh/qRgvaC1Qu47Sjo= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86d27d54-c1ff-46e3-b929-08d6c15bcfc6 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Apr 2019 04:35:39.0014 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4861 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Message-ID: <20190415043538.I5gYTItcUIkUPq9v8y1y_atlIbuXh2sS5B0kOGUpEaY@z> > > > > ---------------------------------------------------------------------- > > Per the email discussion [1], the default cache line size of armv8 > > cortex-a72 is changed to 64 bytes. >=20 > IMO, In git commit you remove the reference to specific discussion and > Update the reason correctly. >=20 >=20 > > > > [1] https://mails.dpdk.org/archives/dev/2019-January/123218.html > > > > Signed-off-by: Yongseok Koh <yskoh@mellanox.com> > > --- > > config/arm/meson.build | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > e00b894523..73c581948c 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ > > ['RTE_MAX_LCORE', 16], > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra > =3D [] > > +flags_cortex_a72_extra =3D [ > > + ['RTE_CACHE_LINE_SIZE', 64]] > > flags_thunderx_extra =3D [ Which tree does this patch apply to? I do not see the above line in master. > > ['RTE_MACHINE', '"thunderx"'], > > ['RTE_USE_C11_MEM_MODEL', false]] > > @@ -73,7 +75,7 @@ machine_args_generic =3D [ > > ['0xd03', ['-mcpu=3Dcortex-a53']], > > ['0xd04', ['-mcpu=3Dcortex-a35']], > > ['0xd07', ['-mcpu=3Dcortex-a57']], > > - ['0xd08', ['-mcpu=3Dcortex-a72']], > > + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], > > ['0xd09', ['-mcpu=3Dcortex-a73']], > > ['0xd0a', ['-mcpu=3Dcortex-a75']]] >=20 > I think, flags_cortex_a72_extra() can be changed to > flags_vendor_arm_extra or something similar And update the following > CPUs also not just cortex-a72. >=20 Why not add 'flags_arm' similar to flags_dpaa2/flag_cavium etc? All the lis= ted Arm cores are 64B cache line size. > ['0xd03', ['-mcpu=3Dcortex-a53']], > ['0xd04', ['-mcpu=3Dcortex-a35']], > ['0xd05', ['-mcpu=3Dcortex-a55']], > ['0xd07', ['-mcpu=3Dcortex-a57']], > ['0xd08', ['-mcpu=3Dcortex-a72']], > ['0xd09', ['-mcpu=3Dcortex-a73']], > ['0xd0a', ['-mcpu=3Dcortex-a75']], > ['0xd0b', ['-mcpu=3Dcortex-a76']], >=20 >=20 > > > > -- > > 2.21.0.196.g041f5ea