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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4944; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: oZf+vDBNf2jHSBmcb0Jz8FDbuA1251w3B/HN5I/bGbn0LDYM5Dd/ebP9+MC6wN+2TqhYHoprUNhuQ1626G47ZL2yLGB6Ovb+koohln0TRUXRFuojo7wlKBoXLVjrpTXSVnp9XN5JA+o1YrC3qr9YHddxzgLT4kKxHs18UmRbhS5SuFtGOJN5SC5va80USqn2qbf1EgBoi32NAxukI0wCdxJAp8dwnBKlPEgJtvW2D7oTBEiOg8YNcQg8xuSIETdR4dn70jfBkyp/TN+Y1s5DqbecgsByGbuuqGNzXKyu3MuwscyZeQAgEzwHBh9EWVlGKIwZzcGAJt+ZGUrYZYY6f7bQzVfk1HuBr1CQu3XB3Qplz/EL0EI3/yI/qQYb49rj/OYmuWoDyhpdJGLCYy0zBITEr/sLmhU+QSpwH9agX9w= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: d730ca43-8f10-425c-bc29-08d6f8becc3d X-MS-Exchange-CrossTenant-originalarrivaltime: 24 Jun 2019 16:12:47.2307 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Honnappa.Nagarahalli@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4944 Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > > > > Add 128-bit atomic compare exchange on aarch64. > > > > > > Signed-off-by: Phil Yang > > > Reviewed-by: Honnappa Nagarahalli > > > Tested-by: Honnappa Nagarahalli > > > --- > > > This patch depends on 'eal/stack: fix 'pointer-sign' warning' > > > http://patchwork.dpdk.org/patch/54840/ > > > > > > + > > > +#ifdef __ARM_FEATURE_ATOMICS > > > +static inline rte_int128_t > > > +__rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t > > > +updated, int mo) { > > > > Better to change to "const int mo". > > > > > + > > > + /* caspX instructions register pair must start from even-numbered > > > + * register at operand 1. > > > + * So, specify registers for local variables here. > > > + */ > > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; > > > + register uint64_t x1 __asm("x1") =3D (uint64_t)old.val[1]; > > > + register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; > > > + register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; > > > + > > > + if (mo =3D=3D __ATOMIC_RELAXED) { > > > + asm volatile( > > > + "casp %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_ACQUIRE) { > > > + asm volatile( > > > + "caspa %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_ACQ_REL) { > > > + asm volatile( > > > + "caspal %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > + } else if (mo =3D=3D __ATOMIC_RELEASE) { > > > + asm volatile( > > > + "caspl %[old0], %[old1], %[upd0], %[upd1], > > > [%[dst]]" > > > + : [old0] "+r" (x0), > > > + [old1] "+r" (x1) > > > + : [upd0] "r" (x2), > > > + [upd1] "r" (x3), > > > + [dst] "r" (dst) > > > + : "memory"); > > > > I think, This duplication code can be avoid with macro and > > casp/capsa/casal/caspl as argument. > > > > > + } else { > > > + rte_panic("Invalid memory order\n"); > > > > > > rte_panic should be removed from library. In this case, I think, > > invalid mo can go for strongest barrier. It is added here to capture programming errors. Memory order can be passed = during compilation or during run time. 'rte_panic' supports both of these. Adding code with strongest memory order will mask the programming error. > > > > > + } > > > + > > > + old.val[0] =3D x0; > > > + old.val[1] =3D x1; > > > + > > > + return old; > > > +} > > > +#else