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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4749; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: KzIx5MdQlGaphwhBAFBOixPxBF4Qn7X26BKPpA/HcNMO9MaMe/3PJeLZRh7ulkj2/9mOJLXxbdV3/d4F7nX1kdTF0jcV4BkzHi85ffNr84b0Nl4BgN+2sxJtTZP5yUYa1o6trwIx3rbMBlX4FCkV8+06VJSCUawJKzuPFh/OmH4XrxCteFaZF5bM9M1LySSc/4rFDtVGS+DOo6FtV3w6PGv32k3lia5VoS30RcATS8UIjKy2tUeXaL4s4b7qVFtwgmYEajGH//Fh7G5UKtZINmZP5/h6W4H1AEZqFLa43W3U2MytiC4d9eNos1KNoA74gVASsb2u+tgmJRNwGUIevGQ81zam6L/2x+Ugt+Uxxa4GzCsOd4MBY+nU1gtpfSwOG5EJ41upIPFT9LwRr6LTaUKk461xJHo3cjS2h72kyxY= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6804383-71af-4059-8336-08d701001fbe X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jul 2019 04:20:33.8622 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Honnappa.Nagarahalli@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB4749 Subject: Re: [dpdk-dev] [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > > > Subject: [EXT] [PATCH v3 1/3] eal/arm64: add 128-bit atomic compare > > > exchange > > > > > > Add 128-bit atomic compare exchange on aarch64. > > > > > > Signed-off-by: Phil Yang > > > Tested-by: Honnappa Nagarahalli > > > Reviewed-by: Honnappa Nagarahalli > > > --- > > > v3: > > > 1. Avoid duplication code with macro. (Jerin Jocob) 2. Make invalid > > > memory order to strongest barrier. (Jerin Jocob) 3. Update > > > doc/guides/prog_guide/env_abstraction_layer.rst. (Eads Gage) 4. Fix > > > 32-bit x86 builds issue. (Eads Gage) 5. Correct documentation issues > > > in UT. (Eads Gage) > > > > > > .../common/include/arch/arm/rte_atomic_64.h | 165 > > > +++++++++++++++++++++ > > > .../common/include/arch/x86/rte_atomic_64.h | 12 -- > > > lib/librte_eal/common/include/generic/rte_atomic.h | 17 ++- > > > 3 files changed, 181 insertions(+), 13 deletions(-) > > > > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > index 97060e4..2080c4d 100644 > > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h > > > @@ -1,5 +1,6 @@ > > > /* SPDX-License-Identifier: BSD-3-Clause > > > * Copyright(c) 2015 Cavium, Inc > > > + * Copyright(c) 2019 Arm Limited > > > */ > > > > > > #ifndef _RTE_ATOMIC_ARM64_H_ > > > @@ -14,6 +15,9 @@ extern "C" { > > > #endif > > > > > > #include "generic/rte_atomic.h" > > > +#include > > > +#include > > > +#include > > > > > > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define > > > dmb(opt) asm volatile("dmb " #opt : : : "memory") @@ -40,6 +44,167 > > > @@ extern "C" { > > > > > > #define rte_cio_rmb() dmb(oshld) > > > > > > +/*------------------------ 128 bit atomic operations > > > +-------------------------*/ > > > + > > > +#define RTE_HAS_ACQ(mo) ((mo) !=3D __ATOMIC_RELAXED && (mo) !=3D > > > +__ATOMIC_RELEASE) #define RTE_HAS_RLS(mo) ((mo) =3D=3D > > __ATOMIC_RELEASE > > > || \ > > > + (mo) =3D=3D __ATOMIC_ACQ_REL || \ > > > + (mo) =3D=3D __ATOMIC_SEQ_CST) > > > + > > > +#define RTE_MO_LOAD(mo) (RTE_HAS_ACQ((mo)) \ > > > + ? __ATOMIC_ACQUIRE : __ATOMIC_RELAXED) #define > > > RTE_MO_STORE(mo) > > > +(RTE_HAS_RLS((mo)) \ > > > + ? __ATOMIC_RELEASE : __ATOMIC_RELAXED) > > > + > > > +#ifdef __ARM_FEATURE_ATOMICS > > > +#define __ATOMIC128_CAS_OP(cas_op_name, op_string) > \ > > > +static inline rte_int128_t = \ > > > +cas_op_name(rte_int128_t *dst, rte_int128_t old, = \ > > > + rte_int128_t updated) = \ > > > +{ = \ > > > + /* caspX instructions register pair must start from even-numbered > > > + * register at operand 1. > > > + * So, specify registers for local variables here. > > > + */ = \ > > > + register uint64_t x0 __asm("x0") =3D (uint64_t)old.val[0]; = \ > > > > I understand CASP limitation on register has to be even and odd. > > Is there anyway to remove explicit x0 register allocation and choose > > compiler to decide the register. Some reason with optimize(03) gcc > > makes correctly but not clang. > > > > Hardcoding to specific register makes compiler to not optimize the > > stuff, especially if it is inline function. >=20 > It look like the limitation fixed recently in gcc. > https://patches.linaro.org/patch/147991/ >=20 > Not sure about old gcc and clang. ARM compiler experts may know the exact > status >=20 We could use syntax as follows, an example is in [1] static inline rte_int128_t __rte_casp(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated, int m= o) { __asm__ volatile("caspl %0, %H0, %1, %H1, [%2]" : "+r" (old) : "r" (updated), "r" (dst) : "memory"); return old; =20 } [1] https://godbolt.org/z/EUJnuG