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Sat, 23 Sep 2017 10:40:02 +0000 From: Shreyansh Jain To: Thomas Monjalon CC: "dev@dpdk.org" , "ferruh.yigit@intel.com" , Hemant Agrawal Thread-Topic: [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD Thread-Index: AQHTM6SXjFzzbNI9MkiPVx8KmnH/JKLA6BKggAAMPICAAVLCoA== Date: Sat, 23 Sep 2017 10:39:57 +0000 Deferred-Delivery: Sat, 23 Sep 2017 10:39:06 +0000 Message-ID: References: <20170823141213.25476-1-shreyansh.jain@nxp.com> <1563275.iJklTzZNDB@xps> <2005912.TG1KxgVreU@xps> In-Reply-To: <2005912.TG1KxgVreU@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-originating-ip: [122.177.191.204] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB4PR04MB0766; 6:a9JY0yiqtXiP6aQGl9qlCY1iN5NTa9dgTGFZNMvWyMEh0uCTBFW/Gir/w+xkfn9IVIvTgN9IzvNqtZtZbMCv7l1oftZKep0l9cWyFkqVVgrQnkIYZhd9ttsWOKYsDMOhkfoWeu8Tl2MRgtOGTAupfTZwsevEPtPqABGzJAmCXoSccPkk8cGetAHeBuyJcdBp/uYnIM+UT+kSi4u0lQZrp8rUWcfWBoqJ8mPBqYcfAXCP5Sl5R1b+s7GTVMTdLtynDuSg7Of78YVpGVq1kiIjpYivQZ0SDugvRlGTo4IHVGlOGI45tY4HkBXhnm/D7PbHqNY+CDw2bgiRvZtjmFBSVQ==; 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DIR:OUT; SFP:1101; SCL:1; SRVR:DB4PR04MB0766; H:VI1PR0401MB2464.eurprd04.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; x-ms-office365-filtering-correlation-id: d33951b9-47ce-4983-67e4-08d5026f7271 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(48565401081)(300000503095)(300135400095)(2017052603199)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:DB4PR04MB0766; x-ms-traffictypediagnostic: DB4PR04MB0766: x-exchange-antispam-report-test: UriScan:(185117386973197)(228905959029699); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123560025)(20161123564025)(20161123562025)(20161123558100)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DB4PR04MB0766; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DB4PR04MB0766; x-forefront-prvs: 0439571D1D received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Sep 2017 10:40:02.5734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR04MB0766 Subject: Re: [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Sep 2017 10:40:05 -0000 > -----Original Message----- > From: Thomas Monjalon [mailto:thomas@monjalon.net] > Sent: Friday, September 22, 2017 7:49 PM > To: Shreyansh Jain > Cc: dev@dpdk.org; ferruh.yigit@intel.com; Hemant Agrawal > > Subject: Re: [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD >=20 > 22/09/2017 16:00, Shreyansh Jain: > > From: Thomas Monjalon [mailto:thomas@monjalon.net] > > > At the beginning of fslmc work, I had understood that every NXP SoC w= ere > > > connecting components with the same principle which we could call the > > > "Freescale bus". > > > Then you came with this bus named bus/fslmc, not bus/dpaa2. > > > Now I am confused. What is the exact scope of fslmc? Is it just DPAA2= ? > > > > My memory is poor. I will have to look through the old emails what happ= ened > - but I recall there was a discussion in initial phases about the naming. > "fslmc" came out as a name that is what is the real name of the DPAA2 bus= . > There was initial a confusion if name of bus in Linux Kernel should match= or > not - but, we realized that bus is *not* device and device name is "dpaa2= ". > > > > As for whether fslmc would cover multiple SoC - that is still true. The= re > are multiple SoCs within the DPAA2 umbrella. LS20XX, LS108X series and so= me > more - all of which use the FSLMC bus (DPAA2 architecture, on FSLMC bus, > having 'dpaa2' devices). > > > > There is another architecture, an old one, which are still popular. Thi= s is > platform type bus which is aptly named 'dpaa' - and here the confusion of= bus > name and device doesn't appear. (DPAA bus, using DPAA architecture, expos= ing > 'dpaa' devices). > > > > Exact scope of FSLMC is just DPAA2 architecture based SoCs. There are m= any > here with new coming up. > > Exact scope of DPAA bus is just DPAA architecture based SoCs. There are > many here. > > > > Does this clear your doubt to some extent? >=20 > Yes it is a lot clearer! Thanks >=20 > Now that I better understand, I think flsmc bus should have been named > dpaa2 bus. Is it too late? :) I resonate your thought that drivers/bus/dpaa2, drivers/mempool/dpaa2, driv= ers/net/dpaa2, drivers/crypto/dpaa2_sec would have been more uniform. But a= gain, that would have misled a lot of DPAA2 users into thinking bus name is= 'dpaa2' which is not the case. And anyways, the changes required in the code to reflect this name change a= re not worthwhile. I would prefer to go as is.