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Fri, 16 Jun 2017 09:21:58 +0000 From: Shreyansh Jain To: Bruce Richardson CC: "dev@dpdk.org" , "ferruh.yigit@intel.com" , Hemant Agrawal Thread-Topic: [dpdk-dev] [PATCH 01/38] eal: add support for 24 40 and 48 bit operations Thread-Index: AQHS5n6UR7jbD+m5XUmH+cR1UqTP9aInNQxA Date: Fri, 16 Jun 2017 09:21:35 +0000 Deferred-Delivery: Fri, 16 Jun 2017 09:20:57 +0000 Message-ID: References: <1497591668-3320-1-git-send-email-shreyansh.jain@nxp.com> <1497591668-3320-2-git-send-email-shreyansh.jain@nxp.com> <20170616085719.GB82628@bricha3-MOBL3.ger.corp.intel.com> In-Reply-To: <20170616085719.GB82628@bricha3-MOBL3.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.88.169.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB4PR04MB0765; 7:ps/OlxSjiGzPqbRTuzVPLsuZQD+Qrs5nTmIFXf6wYqwaQfwZGmujzy5AfIGuAkAlUTi21RsIghts9p3xlWpqS+W3DJB8eP7rFKvtkFg20gSrwgCfJfP8H4rJe4Czx5DAJarrKDStGh6VL2r+sbRVpj/bZ+y7i7d2Y5xSUe0eGOLCCmqC/H8XbhES1O7eaeICpTcYI8/9lPsoKZ8QvnJgXldMH0Qoz/fSmCzxWuEJlZeXU8pU5YsTkSVbFwLCu4sWyuqPOI3PQYlLJ1Gaa6KMigL2wRC6abD50cockR+8R2i+NTgjgFgsOv9jvVxY7hCt0ibKVJK91yWzG1C+nxO+dmWvOnso6xXJZDexwu5em5OR9l8quBab3+E5g1FtGItwzaGen0ogLydMrmqk5daf/w7/vaBbml+nVkNHf0fJDMyzn+8gGG4J/1tkCifwjKLpLJ5P8CLGIAchfAZnRJ24P2Y2A85ACriuaSRKCswVSrFa6e6X30Yjv0dqiWZfYeI/4vKIowSmO1YXFAldtHk4J76yumB5NmEq/Gi7eoIt8U0lRdqvveY596Trc8upeyrY3DJKBKQxjjzemo+OqT4MEWoYiiB8h6AEvQmGJA/M0p+GVTLj7qxXrC9VD4OWbEr8gaQBF9Pf/57b2r0IgbiKj97OHC0UFf7JGYIyGz7HV1fTjVSFLCv9DczmTRAyJWoy0xjiUtm4RUEsdYGkJ/D1oEK2DRsKcWcTB5KX6OTMzqtJiI6muAGEN1v7AwrjIQVLpGpW9PesLIie1uRCiQdt2Ix9l9P4aJ+hTQdk/COwQV4= x-forefront-antispam-report: SFV:SKI; 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x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(10201501046)(100000703101)(100105400095)(3002001)(93006095)(93001095)(6055026)(6041248)(20161123564025)(20161123560025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123562025)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DB4PR04MB0765; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DB4PR04MB0765; x-forefront-prvs: 0340850FCD spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Jun 2017 09:21:58.5576 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR04MB0765 Subject: Re: [dpdk-dev] [PATCH 01/38] eal: add support for 24 40 and 48 bit operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Jun 2017 09:22:01 -0000 Hi Bruce, > -----Original Message----- > From: Bruce Richardson [mailto:bruce.richardson@intel.com] > Sent: Friday, June 16, 2017 2:27 PM > To: Shreyansh Jain > Cc: dev@dpdk.org; ferruh.yigit@intel.com; Hemant Agrawal > > Subject: Re: [dpdk-dev] [PATCH 01/38] eal: add support for 24 40 and 48 b= it > operations >=20 > On Fri, Jun 16, 2017 at 11:10:31AM +0530, Shreyansh Jain wrote: > > From: Hemant Agrawal > > > > Bit Swap and LE<=3D>BE conversions for 23, 40 and 48 bit width > > > > Signed-off-by: Hemant Agrawal > > --- > > .../common/include/generic/rte_byteorder.h | 78 > ++++++++++++++++++++++ > > 1 file changed, 78 insertions(+) > > > Are these really common enough for inclusion in an generic EAL file? > Would they be better being driver specific, so that we don't end up with > lots of extra byte-swap routines for each possible size used by a > driver. =20 Reasoning was to keep all bit/byte swap at a single place and if it is useful for others. >>From DPAA perspective, these macro can be anywhere. In case someone else to= o has use of this (now or in near-future), probably then we can consider this in EAL. Else, if I don't get much responses in a few days, I will shift them to DPAA driver in next version of this series. - Shreyansh