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Fri, 22 Sep 2017 14:01:08 +0000 From: Shreyansh Jain <shreyansh.jain@nxp.com> To: Thomas Monjalon <thomas@monjalon.net> CC: "dev@dpdk.org" <dev@dpdk.org>, "ferruh.yigit@intel.com" <ferruh.yigit@intel.com>, Hemant Agrawal <hemant.agrawal@nxp.com> Thread-Topic: [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD Thread-Index: AQHTM6SXjFzzbNI9MkiPVx8KmnH/JKLA6BKg Date: Fri, 22 Sep 2017 14:00:42 +0000 Deferred-Delivery: Fri, 22 Sep 2017 13:59:45 +0000 Message-ID: <VI1PR0401MB2464B0A73400A9288BC49B5B90670@VI1PR0401MB2464.eurprd04.prod.outlook.com> References: <20170823141213.25476-1-shreyansh.jain@nxp.com> <25531756.sobbYYJFMz@xps> <b4c14448-4925-0c86-7064-8f63753c5895@nxp.com> <1563275.iJklTzZNDB@xps> In-Reply-To: <1563275.iJklTzZNDB@xps> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-originating-ip: [182.69.253.219] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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SRVR:AM3PR04MB0759; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:AM3PR04MB0759; x-forefront-prvs: 0438F90F17 received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Sep 2017 14:01:08.4807 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB0759 Subject: Re: [dpdk-dev] [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <http://dpdk.org/ml/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://dpdk.org/ml/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <http://dpdk.org/ml/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> X-List-Received-Date: Fri, 22 Sep 2017 14:01:11 -0000 Hello Thomas, > -----Original Message----- > From: Thomas Monjalon [mailto:thomas@monjalon.net] > Sent: Friday, September 22, 2017 6:43 PM > To: Shreyansh Jain <shreyansh.jain@nxp.com> > Cc: dev@dpdk.org; ferruh.yigit@intel.com; Hemant Agrawal > <hemant.agrawal@nxp.com> > Subject: Re: [PATCH v4 00/41] Introduce NXP DPAA Bus, Mempool and PMD >=20 > 22/09/2017 15:06, Shreyansh Jain: > > On Friday 22 September 2017 03:40 AM, Thomas Monjalon wrote: > > > 09/09/2017 13:20, Shreyansh Jain: > > >> DPAA, or Datapath Acceleration Architecture [R2], is a set of hardwa= re > > >> components designed for high-speed network packet processing. This > > >> architecture provides the infrastructure to support simplified shari= ng > of > > >> networking interfaces and accelerators by multiple CPU cores, and th= e > > >> accelerators themselves. > > >> > > >> This patchset introduces the following: > > >> 1. DPAA Bus (drivers/bus/dpaa) > > >> The core of DPAA bus is implemented using 3 main hardware blocks: > QMan, > > >> or Queue Manager; BMan, or Buffer Manager and FMan, or Frame Manag= er. > > >> The patches introduce necessary layers to expose the DPAA hardware > > >> blocks for interfacing with RTE framework. > > > > > > I guess these are the same blocks as for DPAA2? > > > They are in drivers/bus/fslmc/ > > > Why introducing yet another bus driver? > > > The fslmc one was supposed to cover any Freescale (NXP (Qualcomm)) So= C. > > > > Forgot to reply to this in previous email: > > > > No, fslmc is not compatible with DPAA. They are completely different > > architectures. > > I am not sure why you have the notion "fslmc one was supposed to cover > > any Freescale (NXP (Qualcomm)) SoC". That is not correct - FSLMC was > > always for supporting DPAA2 which is based on VFIO. DPAA is more closer > > to a platform layout. > > > > And I don't think we should have single "bus/fslmc" just so that it can > > encompass all NXP SoC. I am assuming you didn't mean this :P. >=20 > At the beginning of fslmc work, I had understood that every NXP SoC were > connecting components with the same principle which we could call the > "Freescale bus". > Then you came with this bus named bus/fslmc, not bus/dpaa2. > Now I am confused. What is the exact scope of fslmc? Is it just DPAA2? My memory is poor. I will have to look through the old emails what happened= - but I recall there was a discussion in initial phases about the naming. = "fslmc" came out as a name that is what is the real name of the DPAA2 bus. = There was initial a confusion if name of bus in Linux Kernel should match o= r not - but, we realized that bus is *not* device and device name is "dpaa2= ". As for whether fslmc would cover multiple SoC - that is still true. There a= re multiple SoCs within the DPAA2 umbrella. LS20XX, LS108X series and some = more - all of which use the FSLMC bus (DPAA2 architecture, on FSLMC bus, ha= ving 'dpaa2' devices). There is another architecture, an old one, which are still popular. This is= platform type bus which is aptly named 'dpaa' - and here the confusion of = bus name and device doesn't appear. (DPAA bus, using DPAA architecture, exp= osing 'dpaa' devices). Exact scope of FSLMC is just DPAA2 architecture based SoCs. There are many = here with new coming up. Exact scope of DPAA bus is just DPAA architecture based SoCs. There are man= y here. Does this clear your doubt to some extent?