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Thu, 18 Apr 2019 08:23:57 +0000 From: Hemant Agrawal To: Honnappa Nagarahalli , "yskoh@mellanox.com" , "bruce.richardson@intel.com" , "jerinj@marvell.com" , "pbhagavatula@marvell.com" , "shahafs@mellanox.com" CC: "dev@dpdk.org" , "thomas@monjalon.net" , "Gavin Hu (Arm Technology China)" , nd , nd Thread-Topic: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache line size for armv8 Thread-Index: AQHU9aO76cCoDb0HPEG7ZtrozI9jKqZBlHrA Date: Thu, 18 Apr 2019 08:23:56 +0000 Message-ID: References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418014726.20600-1-yskoh@mellanox.com> <20190418014726.20600-2-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; x-originating-ip: [92.120.1.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0c1b0276-8c06-4ef9-eb20-08d6c3d7339b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +Zxv16a+1lMkjAZCjMXsach4xjX3o3Dn6gqT5MsP50KUj709Suqwdmtp7nxrn5UBoTZzRX6JsAen5AG42044Y5MXsNzyS3wWSb1BvDKkJdRfd2IDYVSiJ3d5EHaqqZxv7K93wZzz587KJvbMmB9L015OAGtZP1FZpFjplMXdbVMsLO+duDrbkn5sylWJTePL8f6d3lom1zpdqasZWCNNlWtTyxeba2b+c+Ne0L8sFZCq6eQFE1JaSrIIOvwF+mDBLLcCTO50bflBtlEC5blNRPNgsGC6Zjoh1DgIgJiuj6jlY2OlRGwoeyMerEHWFc5twPPORnYiCKo5457WFQ9JTfcj5aFSMXXMy2/a5AlQESy+HpzC6J25pSlipqMe84FBwkYaVkWZIVdZC098/dMKsutkCT+C3aipHn0Z1np8cz0= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0c1b0276-8c06-4ef9-eb20-08d6c3d7339b X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Apr 2019 08:23:56.9734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2653 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v2 2/4] meson: change default cache line size for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 Apr 2019 08:23:58 -0000 > -----Original Message----- > From: dev On Behalf Of Honnappa Nagarahalli > Sent: Thursday, April 18, 2019 10:31 AM > To: yskoh@mellanox.com; bruce.richardson@intel.com; jerinj@marvell.com; > pbhagavatula@marvell.com; shahafs@mellanox.com > Cc: dev@dpdk.org; thomas@monjalon.net; Gavin Hu (Arm Technology > China) ; Honnappa Nagarahalli > ; nd ; nd > Subject: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache > line size for armv8 >=20 =20 > > > > Currently, the cache line size of armv8 CPUs having Implementor ID of > > 0x41 is > > 64 bytes. > I guess you meant to say 128 bytes "the current default is 128, changing it to 64." =20 >=20 > > > > Signed-off-by: Yongseok Koh > > --- > > > > v2: > > * introduce flags_arm replacing flags_generic instead of using the > > extra flags > > > > config/arm/meson.build | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > 22a062bad9..1db4ad2ee7 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -32,6 +32,11 @@ flags_generic =3D [ > > ['RTE_MAX_LCORE', 256], > > ['RTE_USE_C11_MEM_MODEL', true], > > ['RTE_CACHE_LINE_SIZE', 128]] > > +flags_arm =3D [ > > + ['RTE_MACHINE', '"armv8a"'], > > + ['RTE_MAX_LCORE', 256], > I am not aware of any implementations with implementor ID 0x41. Bluefield > is the first one I am aware of. May be we can keep this smaller, 16? NXP also support implementer as 0x41, 16 will be good.=20 >=20 > > + ['RTE_USE_C11_MEM_MODEL', true], > > + ['RTE_CACHE_LINE_SIZE', 64]] > > flags_cavium =3D [ > > ['RTE_CACHE_LINE_SIZE', 128], > > ['RTE_MAX_NUMA_NODES', 2], > > @@ -88,7 +93,7 @@ machine_args_cavium =3D [ > > > > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page > > G7-5321) impl_generic =3D ['Generic armv8', flags_generic, > > machine_args_generic] > > -impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] > > +impl_0x41 =3D ['Arm', flags_arm, machine_args_generic] > > impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] > > impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] > > impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] > > -- > > 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id D8243A00E6 for ; Thu, 18 Apr 2019 10:23:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A7EA71B904; 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Thu, 18 Apr 2019 08:23:57 +0000 From: Hemant Agrawal To: Honnappa Nagarahalli , "yskoh@mellanox.com" , "bruce.richardson@intel.com" , "jerinj@marvell.com" , "pbhagavatula@marvell.com" , "shahafs@mellanox.com" CC: "dev@dpdk.org" , "thomas@monjalon.net" , "Gavin Hu (Arm Technology China)" , nd , nd Thread-Topic: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache line size for armv8 Thread-Index: AQHU9aO76cCoDb0HPEG7ZtrozI9jKqZBlHrA Date: Thu, 18 Apr 2019 08:23:56 +0000 Message-ID: References: <20190412232451.30197-1-yskoh@mellanox.com> <20190418014726.20600-1-yskoh@mellanox.com> <20190418014726.20600-2-yskoh@mellanox.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=hemant.agrawal@nxp.com; x-originating-ip: [92.120.1.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0c1b0276-8c06-4ef9-eb20-08d6c3d7339b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: +Zxv16a+1lMkjAZCjMXsach4xjX3o3Dn6gqT5MsP50KUj709Suqwdmtp7nxrn5UBoTZzRX6JsAen5AG42044Y5MXsNzyS3wWSb1BvDKkJdRfd2IDYVSiJ3d5EHaqqZxv7K93wZzz587KJvbMmB9L015OAGtZP1FZpFjplMXdbVMsLO+duDrbkn5sylWJTePL8f6d3lom1zpdqasZWCNNlWtTyxeba2b+c+Ne0L8sFZCq6eQFE1JaSrIIOvwF+mDBLLcCTO50bflBtlEC5blNRPNgsGC6Zjoh1DgIgJiuj6jlY2OlRGwoeyMerEHWFc5twPPORnYiCKo5457WFQ9JTfcj5aFSMXXMy2/a5AlQESy+HpzC6J25pSlipqMe84FBwkYaVkWZIVdZC098/dMKsutkCT+C3aipHn0Z1np8cz0= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0c1b0276-8c06-4ef9-eb20-08d6c3d7339b X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Apr 2019 08:23:56.9734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0401MB2653 Subject: Re: [dpdk-dev] [EXT] Re: [PATCH v2 2/4] meson: change default cache line size for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190418082356.4rqyhuY4CSKDR9X38mdgQZaBufYBsySSTb57zRHtzxk@z> > -----Original Message----- > From: dev On Behalf Of Honnappa Nagarahalli > Sent: Thursday, April 18, 2019 10:31 AM > To: yskoh@mellanox.com; bruce.richardson@intel.com; jerinj@marvell.com; > pbhagavatula@marvell.com; shahafs@mellanox.com > Cc: dev@dpdk.org; thomas@monjalon.net; Gavin Hu (Arm Technology > China) ; Honnappa Nagarahalli > ; nd ; nd > Subject: [EXT] Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache > line size for armv8 >=20 =20 > > > > Currently, the cache line size of armv8 CPUs having Implementor ID of > > 0x41 is > > 64 bytes. > I guess you meant to say 128 bytes "the current default is 128, changing it to 64." =20 >=20 > > > > Signed-off-by: Yongseok Koh > > --- > > > > v2: > > * introduce flags_arm replacing flags_generic instead of using the > > extra flags > > > > config/arm/meson.build | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/config/arm/meson.build b/config/arm/meson.build index > > 22a062bad9..1db4ad2ee7 100644 > > --- a/config/arm/meson.build > > +++ b/config/arm/meson.build > > @@ -32,6 +32,11 @@ flags_generic =3D [ > > ['RTE_MAX_LCORE', 256], > > ['RTE_USE_C11_MEM_MODEL', true], > > ['RTE_CACHE_LINE_SIZE', 128]] > > +flags_arm =3D [ > > + ['RTE_MACHINE', '"armv8a"'], > > + ['RTE_MAX_LCORE', 256], > I am not aware of any implementations with implementor ID 0x41. Bluefield > is the first one I am aware of. May be we can keep this smaller, 16? NXP also support implementer as 0x41, 16 will be good.=20 >=20 > > + ['RTE_USE_C11_MEM_MODEL', true], > > + ['RTE_CACHE_LINE_SIZE', 64]] > > flags_cavium =3D [ > > ['RTE_CACHE_LINE_SIZE', 128], > > ['RTE_MAX_NUMA_NODES', 2], > > @@ -88,7 +93,7 @@ machine_args_cavium =3D [ > > > > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page > > G7-5321) impl_generic =3D ['Generic armv8', flags_generic, > > machine_args_generic] > > -impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] > > +impl_0x41 =3D ['Arm', flags_arm, machine_args_generic] > > impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] > > impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] > > impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] > > -- > > 2.11.0