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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: d1ba86fb-7171-4aa2-dd39-08d7e23c92aa X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Apr 2020 19:30:08.2201 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ltn36dGuSBMubsEDN8fVZ5C6yQxtp1L5Rt3ijOi/Lk0pcZzhB0NW0j9b76tTlrVFK/1NZOU2xxMXz0Zfsr70rg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5071 Subject: Re: [dpdk-dev] [PATCH v2 10/13] baseband/fpga_5gnr_fec: add configure function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > diff --git a/drivers/baseband/fpga_5gnr_fec/Makefile > b/drivers/baseband/fpga_5gnr_fec/Makefile > index 3f5c511..b68a79f 100644 > --- a/drivers/baseband/fpga_5gnr_fec/Makefile > +++ b/drivers/baseband/fpga_5gnr_fec/Makefile > @@ -23,4 +23,7 @@ LIBABIVER :=3D 1 > # library source files > SRCS-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC) +=3D > rte_fpga_5gnr_fec.c >=20 > +# export include files > +SYMLINK-$(CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC)-include +=3D > fpga_5gnr_fec.h > + > include $(RTE_SDK)/mk/rte.lib.mk > diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > new file mode 100644 > index 0000000..7eebc7d > --- /dev/null > +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h > @@ -0,0 +1,74 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2020 Intel Corporation > + */ > + > +#ifndef _FPGA_5GNR_FEC_H_ > +#define _FPGA_5GNR_FEC_H_ > + > +#include > +#include > + > +/** > + * @file fpga_5gnr_fec.h > + * > + * Interface for Intel(R) FGPA 5GNR FEC device configuration at the host= level, > + * directly accessible by the application. > + * Configuration related to 5GNR functionality is done through > + * librte_bbdev library. > + * > + * @warning > + * @b EXPERIMENTAL: this API may change without prior notice > + */ The exposed PMD header files are normally prefixed as rte_pmd_ You should rename your other header file as fpga_5gnr_fec.h And this one as rte_pmd_fpga_5gnr_fec.h BTW what is the need of a pmd API to configure the fpga? Is it not possible to do that as one of rte_bbdev_ops ? I can see that the comments in rte_bbdev_ops are not in proper format. '<' should not be there if comment is before the element Could you please correct them in a separate patch? Please check other struc= tures as well > + > +#ifdef __cplusplus > +extern "C" { > +#endif > + > +/**< Number of Virtual Functions FGPA 4G FEC supports */ > +#define FPGA_5GNR_FEC_NUM_VFS 8 > + > +/** > + * Structure to pass FPGA 4G FEC configuration. > + */ > +struct fpga_5gnr_fec_conf { > + /**< 1 if PF is used for dataplane, 0 for VFs */ > + bool pf_mode_en; > + /**< Number of UL queues per VF */ > + uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS]; > + /**< Number of DL queues per VF */ > + uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS]; > + /**< UL bandwidth. Needed for schedule algorithm */ > + uint8_t ul_bandwidth; > + /**< DL bandwidth. Needed for schedule algorithm */ > + uint8_t dl_bandwidth; > + /**< UL Load Balance */ > + uint8_t ul_load_balance; > + /**< DL Load Balance */ > + uint8_t dl_load_balance; > + /**< FLR timeout value */ > + uint16_t flr_time_out; If you are adding comment before the element, then no need to add '<'