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Thu, 16 Apr 2020 18:43:38 +0000 Received: from VI1PR04MB3168.eurprd04.prod.outlook.com ([fe80::8c03:2f5:3b48:ba74]) by VI1PR04MB3168.eurprd04.prod.outlook.com ([fe80::8c03:2f5:3b48:ba74%7]) with mapi id 15.20.2921.027; Thu, 16 Apr 2020 18:43:38 +0000 From: Akhil Goyal To: Nicolas Chautru , "dev@dpdk.org" CC: "bruce.richardson@intel.com" Thread-Topic: [PATCH v2 12/13] baseband/fpga_5gnr_fec: add interrupt support Thread-Index: AQHWBia24rC+DBSy/kOxjDQWfPBTFqh8LqLg Date: Thu, 16 Apr 2020 18:43:38 +0000 Message-ID: References: <1585526580-113508-1-git-send-email-nicolas.chautru@intel.com> <1585526580-113508-13-git-send-email-nicolas.chautru@intel.com> In-Reply-To: <1585526580-113508-13-git-send-email-nicolas.chautru@intel.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=akhil.goyal@nxp.com; x-originating-ip: [45.118.166.95] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: acc91d76-024c-4506-e8f9-08d7e23613b9 x-ms-traffictypediagnostic: VI1PR04MB7053: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6108; x-forefront-prvs: 0375972289 x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR04MB3168.eurprd04.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(10009020)(4636009)(39860400002)(346002)(376002)(136003)(366004)(396003)(6506007)(186003)(44832011)(8936002)(64756008)(66946007)(66476007)(76116006)(5660300002)(81156014)(55016002)(66556008)(8676002)(4326008)(110136005)(66446008)(478600001)(86362001)(26005)(316002)(52536014)(9686003)(2906002)(33656002)(71200400001)(7696005); DIR:OUT; SFP:1101; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: oqmZPd6KaHdkxrFEZR/JLoZFK9gj4FJEhbbqJBINRCvhVgpaTr8dxK6ncxjydJHPxGLuPZBunbgOPJeYnMX+yDpxpuLphsU3EZRVKQ2e9nS2UPFthecX3WrwA17VPxp9jZy8yF0Q780O9yW3BQcxJmwRkPxodBgFtX+PZW5Y43G7/nzH0U/7xacoQdQhiBgjJ+Ky34B1bE8OtPzPVPhIEt4Gr8s+H4qDco8LeTyIHoGt4A8H2XBvS5gAsUb8NE3xptzQCvFqMCi8WR1htU7QjFrEBujahcAPo63qbl4eJya3ayEcnh4mSJo2WYh2pHp61rjfGWOlR5BQfI8jo99kusWi0e8PHT/KVvG78r0AdlLfPY+iOcsAzA1JMnwqvIU3YGzoqRFv2KP6T4XjnobhMHv7rpNfUKYdkv/GSGe0O0ChmXO6ptf1MYqyab3Y9W5G x-ms-exchange-antispam-messagedata: /g+kdlhShiZYYYBo4tbVFdlRD1eZiD0gR0ee2aYps4W4XEjX3ia/wlfW3A3aqT3knxtiv/DugIsgEPMqOKJAy2wsAGNjTIciLEBY9DzTqPi9b+bC83MmXUiXz62e+16qphbQ+fbk/5tzD0L8BQjRYQ== x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: acc91d76-024c-4506-e8f9-08d7e23613b9 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Apr 2020 18:43:38.2247 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dyUSv/JrCMUi12tzJtmK0OdLUYQN8YSCjMNBrv4pXYvXHGVKMqLyuyY99DNgGDn+YoA+iJ4Uh9mgvtIgd04tLw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7053 Subject: Re: [dpdk-dev] [PATCH v2 12/13] baseband/fpga_5gnr_fec: add interrupt support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Adding support for interrupt capability in the PMD > and the related operations. >=20 > Signed-off-by: Nicolas Chautru > --- > drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 156 > +++++++++++++++++++++ > 1 file changed, 156 insertions(+) >=20 > diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > index b8cad1a..45a3126 100644 > --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c > @@ -110,6 +110,23 @@ > return rte_le_to_cpu_32(ret); > } >=20 > +/* Read a register of FPGA 5GNR FEC device */ > +static uint8_t > +fpga_reg_read_8(void *mmio_base, uint32_t offset) > +{ > + void *reg_addr =3D RTE_PTR_ADD(mmio_base, offset); > + return *((volatile uint8_t *)(reg_addr)); > +} > + > +/* Read a register of FPGA 5GNR FEC device */ > +static uint64_t > +fpga_reg_read_64(void *mmio_base, uint32_t offset) > +{ > + void *reg_addr =3D RTE_PTR_ADD(mmio_base, offset); > + uint64_t ret =3D *((volatile uint64_t *)(reg_addr)); > + return rte_le_to_cpu_64(ret); > +} > + Above reg_read APIs should be moved in the header file and made as inline a= long with all others in your 6/13 patch.