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Sat, 9 Mar 2019 10:28:57 +0000 From: "Gavin Hu (Arm Technology China)" To: Honnappa Nagarahalli , "thomas@monjalon.net" , "Ananyev, Konstantin" CC: Ilya Maximets , "dev@dpdk.org" , nd , "jerinj@marvell.com" , "hemant.agrawal@nxp.com" , "Nipun.gupta@nxp.com" , "olivier.matz@6wind.com" , "Richardson, Bruce" , "chaozhu@linux.vnet.ibm.com" , nd Thread-Topic: [PATCH v2] ring: enforce reading the tails before ring operations Thread-Index: AQHU1LF27vtsQ2Xy+0iZsAZL3+5RW6X/3LWAgAAItaCAAAb/gIAADMAQgAEUeFCAAJmlgIAALgYQgAAOnACAAH0WAIAACFgAgACxm+A= Date: Sat, 9 Mar 2019 10:28:57 +0000 Message-ID: References: <1551841661-42892-1-git-send-email-gavin.hu@arm.com> <2601191342CEEE43887BDE71AB9772580136556F40@irsmsx105.ger.corp.intel.com> <2456717.RLOWIjrx09@xps> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Gavin.Hu@arm.com; x-originating-ip: [113.29.88.7] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cb9ffafc-1e46-4b94-ad71-08d6a47a09a2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR08MB2974; H:VI1PR08MB3167.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: LcgKg3GxWj2eriiicl/GG87JhLEc+SEZf3oPs4zV6jaB9WP7UXAcjrJJOGZe8V/xCpvSHFLQ1PN+u9gwMfZkGklnEDchC0qp67S+BlTyhQYTcW3mZEU8gN57KZnWC9UH/HLpWEk2y8VRlEc5fO1fILNJvNMNclfQ8jc/4xLH8nfYfI/pMxLrg8QEaXji0QEulaxPAY/Kd6qdVO477TB0RKFIkHDgEuvvnzalprN0Uqvm/aA45CpV9KFdQUyo+0rAhNj/vu6SHyVy2wYdW06D5ZVv+8OdQUR2cha1IFnn2P37eNiAVn8nWdpEGyQPgU1w+5bW2FpLDW5WexXZgMHHaYEpmn6l40JLpMTXE7qG1pGX23A/Z0tNqrDTXElkxytuozXBz41kUrevP9KQzrOSRdx6XdjJO6oIUqip7LiSZ3Y= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: cb9ffafc-1e46-4b94-ad71-08d6a47a09a2 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Mar 2019 10:28:57.1463 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB2974 Subject: Re: [dpdk-dev] [PATCH v2] ring: enforce reading the tails before ring operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 09 Mar 2019 10:29:00 -0000 > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Saturday, March 9, 2019 7:48 AM > To: thomas@monjalon.net; Ananyev, Konstantin > ; Gavin Hu (Arm Technology China) > > Cc: Ilya Maximets ; dev@dpdk.org; nd > ; jerinj@marvell.com; hemant.agrawal@nxp.com; > Nipun.gupta@nxp.com; olivier.matz@6wind.com; Richardson, Bruce > ; chaozhu@linux.vnet.ibm.com; nd > > Subject: RE: [PATCH v2] ring: enforce reading the tails before ring > operations >=20 > > 08/03/2019 16:50, Ananyev, Konstantin: > > > 08/03/2019 16:05, Gavin Hu (Arm Technology China): > > > > Anyway, on x86, smp_rmb, as a compiler barrier, applies to > load/store, not > > only load/load. > > > > > > Yes, that's true, but I think that's happened by coincidence, not > > > intentionally. > > > > > > > This is the case also for arm, arm64, ppc32, ppc64. > > > > I will submit a patch to expand the definition of this API. > > > > > > I understand your intention, but that does mean we would also need > to > > > change not only rte_smp_rmb() but rte_rmb() too (to keep things > consistent)? > > > That sounds worring. > > > Might be better to keep smp_rmb() definition as it is, and introduce > > > new function that fits your purposes (smp_rwmb or > smp_load_store_barrier)? > Looking at rte_rmb, rte_io_rmb, rte_cio_rmb implementations for Arm, > they all provide load/store barrier as well. If other architectures also > provide load/store barrier with rte_xxx_rmb, then we could extend the > meaning of the existing APIs. Further looking at rte_rmb, rte_io_rmb, rte_cio_rmb implementations for PPC= 64 and x86, They also provide load/store barrier. It is safe to extend the meaning of t= he existing rte_XXX_rmb API. >=20 > Even if a new API is provided, we need to do provide the same APIs for IO > and CIO variants. Since rte_XXX_rmbs API for all architectures already provide the desired lo= ad/store ordering, a new API is redundant and not needed.=20 > > > > How is it managed in other projects? > In my experience, I usually have been changing the algorithms to use C11 > memory model. So, I have not come across this issue yet. Others can > comment. >=20 > >