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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0801MB2051 Subject: Re: [dpdk-dev] [PATCH v2 17/17] net/hinic: optimize tx&rx performance X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Xiaoyun, > -----Original Message----- > From: dev On Behalf Of Xiaoyun wang > Sent: Wednesday, September 25, 2019 10:31 PM > To: ferruh.yigit@intel.com > Cc: dev@dpdk.org; xuanziyang2@huawei.com; shahar.belkar@huawei.com; > luoxianjun@huawei.com; tanya.brokhman@huawei.com; > zhouguoyang@huawei.com; wulike1@huawei.com; Xiaoyun wang > > Subject: [dpdk-dev] [PATCH v2 17/17] net/hinic: optimize tx&rx > performance >=20 > This patch optimizes receive packets performance > in arm platform. >=20 > Signed-off-by: Xiaoyun wang > --- > drivers/net/hinic/hinic_pmd_rx.c | 17 +++++++++++++++++ > drivers/net/hinic/hinic_pmd_rx.h | 11 +++++++++++ > 2 files changed, 28 insertions(+) >=20 > diff --git a/drivers/net/hinic/hinic_pmd_rx.c > b/drivers/net/hinic/hinic_pmd_rx.c > index 37b4f5c..94071ee 100644 > --- a/drivers/net/hinic/hinic_pmd_rx.c > +++ b/drivers/net/hinic/hinic_pmd_rx.c > @@ -950,6 +950,19 @@ void hinic_rx_alloc_pkts(struct hinic_rxq *rxq) > } > } >=20 > +#if defined(__ARM64_NEON__) No NEON intrinsics used, maybe RTE_ARCH_ARM64 is better.=20 In the following line __rte_always_inline is commonly used in DPDK, the eff= ect is same. /Gavin > +static inline uint32_t __attribute__((always_inline)) > +hinic_read_cqe_status(uintptr_t addr) > +{ > + uint32_t val; > + > + asm volatile("ldar %x[val], [%x[addr]]" > + : [val] "=3Dr" (val) > + : [addr] "r" (addr)); > + return val; > +} > +#endif I understand your intention is the reading of the status is observed before= the following reads. This can be fulfilled by __atomic_load_n(...) with __ATOMIC_ACQUIRE semanti= cs.=20 This C11 way applies to all the arches, and you don't need the differentiat= ion of arches.=20 /Gavin > + > u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 > nb_pkts) > { > struct rte_mbuf *rxm; > @@ -972,7 +985,11 @@ u16 hinic_recv_pkts(void *rx_queue, struct > rte_mbuf **rx_pkts, u16 nb_pkts) > while (pkts < nb_pkts) { > /* 2. current ci is done */ > rx_cqe =3D &rxq->rx_cqe[sw_ci]; > +#if defined(__X86_64_SSE__) > status =3D rx_cqe->status; > +#elif defined(__ARM64_NEON__) > + status =3D hinic_read_cqe_status((uintptr_t)&rxq- > >rx_cqe[sw_ci]); > +#endif > if (!HINIC_GET_RX_DONE_BE(status)) > break; >=20 > diff --git a/drivers/net/hinic/hinic_pmd_rx.h > b/drivers/net/hinic/hinic_pmd_rx.h > index fe2735b..fa27e91 100644 > --- a/drivers/net/hinic/hinic_pmd_rx.h > +++ b/drivers/net/hinic/hinic_pmd_rx.h > @@ -28,6 +28,7 @@ struct hinic_rq_ctrl { > u32 ctrl_fmt; > }; >=20 > +#if defined(__X86_64_SSE__) > struct hinic_rq_cqe { > u32 status; > u32 vlan_len; > @@ -36,6 +37,16 @@ struct hinic_rq_cqe { >=20 > u32 rsvd[4]; > }; > +#elif defined(__ARM64_NEON__) > +struct hinic_rq_cqe { > + u32 status; > + u32 vlan_len; > + u32 offload_type; > + u32 rss_hash; > + > + u32 rsvd[4]; > +} __rte_cache_aligned; > +#endif >=20 > struct hinic_rq_cqe_sect { > struct hinic_sge sge; > -- > 1.8.3.1