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X-Microsoft-Antispam-Message-Info: efQlAuYtoqhpwHrJiZom9q5XRFW1GAtlzudiDGh6NiqL8QAo/aSZVGDKHa3VRVLTtcJZfXOcWKm4uldDTAzWFf3+mwLFukWPSsWWjzs23TJJLGE1fE2PeXi+LG4D87An3hzAPqpXRTbRh6KWiq+187iRpnfRxp0LEbc3qAJnO645dFDIMlq76o5s1gLe2A3cXYmwXBAw8i7s/cyNCck7OHnD9Tt5YvAPwMqpC+dclwR06HyVNfiCdtjYtBilBMzqajkxIJ88qsfWXTUS1wFp1+lt+BLPlh9zahImzeDByt6WOnxQ3VqF9MYh/OYQpH1MwnPagovNaPsTS3esr3ADsEMyRIr2QtonPpfOmadyB+2Do046f/4pPEdfU4Q9jFC/ZGQVMtYQV8XNAaVPvMpQzWdP4/KGlh1PQzKExIrO36DipLyirZTjI+iSuPZYsGeZfqSNFH4aMf4NjiHYXJYQNknsSNtWTsnYYSsbdztkNSA= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2019 09:12:50.9260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dc5680d-5b90-4d24-2289-08d75abdd7ad X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB5242 Subject: Re: [dpdk-dev] [PATCH] event/octeontx2: use wfe while waiting for head X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Pavan, > -----Original Message----- > From: Pavan Nikhilesh Bhagavatula > Sent: Saturday, October 26, 2019 1:06 AM > To: Gavin Hu (Arm Technology China) ; > jerinj@marvell.com > Cc: dev@dpdk.org; nd ; nd > Subject: RE: [dpdk-dev] [PATCH] event/octeontx2: use wfe while waiting fo= r > head >=20 > Hi Gavin, > >Hi Pavan, > > > >> -----Original Message----- > >> From: Pavan Nikhilesh Bhagavatula > >> Sent: Friday, October 25, 2019 12:26 PM > >> To: Gavin Hu (Arm Technology China) ; > >> jerinj@marvell.com > >> Cc: dev@dpdk.org; nd > >> Subject: RE: [dpdk-dev] [PATCH] event/octeontx2: use wfe while > >waiting for > >> head > >> > >> Hi Gavin, > >> > >> >-----Original Message----- > >> >From: dev On Behalf Of Gavin Hu (Arm > >> >Technology China) > >> >Sent: Thursday, October 24, 2019 9:23 PM > >> >To: Pavan Nikhilesh Bhagavatula ; > >Jerin > >> >Jacob Kollanukkaran > >> >Cc: dev@dpdk.org; nd > >> >Subject: Re: [dpdk-dev] [PATCH] event/octeontx2: use wfe while > >> >waiting for head > >> > > >> >Hi Pavan, > >> > > >> >> -----Original Message----- > >> >> From: pbhagavatula@marvell.com > >> >> Sent: Thursday, October 24, 2019 12:13 AM > >> >> To: Gavin Hu (Arm Technology China) ; > >> >> jerinj@marvell.com; Pavan Nikhilesh > > > >> >> Cc: dev@dpdk.org > >> >> Subject: [dpdk-dev] [PATCH] event/octeontx2: use wfe while > >waiting > >> >for > >> >> head > >> >> > >> >> From: Pavan Nikhilesh > >> >> > >> >> Use wfe to save power while waiting for tag to become head. > >> >> > >> >> SSO signals EVENTI to allow cores to exit from wfe when they > >> >> are waiting for specific operations in which one of them is > >> >> setting HEAD bit in GWS_TAG. > >> >> > >> >> Signed-off-by: Pavan Nikhilesh > >> >> --- > >> >> drivers/event/octeontx2/otx2_worker.h | 30 > >> >++++++++++++++++++++++++-- > >> >> - > >> >> 1 file changed, 27 insertions(+), 3 deletions(-) > >> >> > >> >> diff --git a/drivers/event/octeontx2/otx2_worker.h > >> >> b/drivers/event/octeontx2/otx2_worker.h > >> >> index 4e971f27c..7a55caca5 100644 > >> >> --- a/drivers/event/octeontx2/otx2_worker.h > >> >> +++ b/drivers/event/octeontx2/otx2_worker.h > >> >> @@ -226,10 +226,34 @@ otx2_ssogws_swtag_wait(struct > >> >otx2_ssogws *ws) > >> >> } > >> >> > >> >> static __rte_always_inline void > >> >> -otx2_ssogws_head_wait(struct otx2_ssogws *ws, const uint8_t > >> >wait_flag) > >> >> +otx2_ssogws_head_wait(struct otx2_ssogws *ws) > >> >> { > >> >> - while (wait_flag && !(otx2_read64(ws->tag_op) & > >> >BIT_ULL(35))) > >> >> +#ifdef RTE_ARCH_ARM64 > >> >> + uint64_t tag; > >> >> + > >> >> + asm volatile ( > >> >> + " ldr %[tag], [%[tag_op]] \n" > >> >"ldxr" should be used, exclusive-load is required to "monitor" the > >> >location, then a write to the location will cause clear of the exclus= ive > >> >monitor, thus a wake up event is generated implicitly. > >> > >> As I have mentioned in the commit log: > >> "SSO signals EVENTI to allow cores to exit from wfe when they > >> are waiting for specific operations in which one of them is > >> setting HEAD bit in GWS_TAG." > >If you have other expected wake up sources, that is ok. Just curious is > >this signal explicitly sent to quit WFE? >=20 > AFAIK yes, explicitly sent to quit WFE. >=20 > >Just wondering, implicit event(Clear of exclusive monitor) vs explicit > >signal, which has shorter latency? >=20 > Not really sure but SSO has dedicated bus inside each core. That's ok. >=20 > >/Gavin > >> > >> The address need not be tracked by the global monitor. > >> > >> >You can find more explanation is here: > >> >https://urldefense.proofpoint.com/v2/url?u=3Dhttp- > >> > >>3A__inbox.dpdk.org_dev_AM0PR08MB5363F9D1BA158B66B803EA068 > >F > >> >6B0- > >> > >>40AM0PR08MB5363.eurprd08.prod.outlook.com_&d=3DDwIFAg&c=3DnKj > >W > >> > >>ec2b6R0mOyPaz7xtfQ&r=3D1cjuAHrGh745jHNmj2fD85sUMIJ2IPIDsIJzo6 > >F > >> >N6Z0&m=3DJMzT-4V2megNsFYxaO0V2wE0- > >> >GlK9UPUvE1K0pPA9aQ&s=3DJajU2VklhV_jFE0WKAZ076KjjWymIC- > >> >iTiJXU0Vwxr4&e=3D > >> >/Gavin > >> >> + " tbnz %[tag], 35, done%=3D > >> > \n" > >> >> + " sevl \n" > >> >> + "rty%=3D: wfe \n" > >> >> + " ldr %[tag], [%[tag_op]] \n" > >> >> + " tbz %[tag], 35, rty%=3D \n" > >> >> + "done%=3D: \n" > >> >> + : [tag] "=3D&r" (tag) > >> >> + : [tag_op] "r" (ws->tag_op) > >> >> + ); > >> >> +#else > >> >> + /* Wait for the HEAD to be set */ > >> >> + while (!(otx2_read64(ws->tag_op) & BIT_ULL(35))) > >> >> ; > >> >> +#endif > >> >> +} > >> >> + > >> >> +static __rte_always_inline void > >> >> +otx2_ssogws_order(struct otx2_ssogws *ws, const uint8_t > >> >wait_flag) > >> >> +{ > >> >> + if (wait_flag) > >> >> + otx2_ssogws_head_wait(ws); > >> >> > >> >> rte_cio_wmb(); > >> >What ordering does this barrier try to keep? If there is a write the= n > >wait > >> >for kind of response, should this barrier move before > >> >otx2_ssogws_head_wait? > >> > >> The barrier is used to flush out write buffer to LLC (octeontx2 point = of > >> coherence) so > >> that NIX Tx picks up all the modifications done to the packet. >=20 > >Looking at the otx2_ssogws_event_tx function, so far at the point of > >rte_cio_wmb, only the header is written? > >Should it be delayed after the whole packet written and before the > >submission? >=20 > We only care that the writes to the actual packet buffer ex. Start of eth= ernet > header > are committed. > The rest of mbuf fields are translated into a HW command after the barrie= r > and written > to a LMTLINE using ldoer. >=20 > >If NIX is not falling within the SMP configuration, should it be > >rte_io_wmb instead? >=20 > Octeontx2 has only single shareability domain i.e. it makes no distinctio= n > between > Outer and inner sharable domains. > Since all IO devices are interpreted to be on outer sharable domain, we l= ike > to use > rte_cio_(r/w)mb for IO devices. Yes, for an integral part of the out sharable domain, rte_cio_(r/w)mb is su= fficient.=20 >=20 > Regards, > Pavan. >=20 > >> >> } > >> >> @@ -258,7 +282,7 @@ otx2_ssogws_event_tx(struct otx2_ssogws > >> >*ws, > >> >> struct rte_event ev[], > >> >> > >> >> /* Perform header writes before barrier for TSO */ > >> >> otx2_nix_xmit_prepare_tso(m, flags); > >> >> - otx2_ssogws_head_wait(ws, !ev->sched_type); > >> >> + otx2_ssogws_order(ws, !ev->sched_type); > >> >> otx2_ssogws_prepare_pkt(txq, m, cmd, flags); > >> >> > >> >> if (flags & NIX_TX_MULTI_SEG_F) { > >> >> -- > >> >> 2.17.1 Reviewed-by: Gavin Hu